Hi, I'm designing a circuit which uses a jfet switch. I am having problems with the jfet on/off time - which seems to be totally inconsistent with the simulation. Attached is a screenshot of my simulation with the scope showing the gate pulse and the output from the drain to ground. This shows a very short on/off time, in the order of 100 nS or so. Also attached is a scope shot of the actual circuit, which shows much longer on/off times of about 40-50 uS

I am interested in the point where the gate pulse goes low turning off the fet, and the output voltage starts to rise to 5v. I need this time to be as small as possible. I can only affect it by making the resistance from drain to ground/+5 smaller but this is unfortunately not acceptable for my circuit. If I completely remove the resistor so the drain to source is only the 1M completely supplied by the resistance of the scope then the rise time is in the order of hundreds of uS.

why am I seeing this negative spike? I thought maybe it was from the capacitance of the gate but the signal source I am driving it from is quite capable of producing enough current to charge the gate in a far shorter time..

any suggestions would be much appreciated

Philip

 

You are using a 1x probe, which has a typical capacitance of 100pF or more. This one is 200pF. This capacitance in parallel with 100k is the reason your risetime is so slow. The 10% to 90% risetime will be 2.2* R*C.
The negative spike is caused by the gate signal coupling through the gate-to-drain capacitance.
A 10x probe will give you better risetime, but the real results will be determined by the cap loading on the drain when the circuit is in actual use.
Why are you using a JFET as a switch? There may be another way of solving your problem.
What are the voltages (high and low) of your gate drive signal?

 

The 100k drain resistor value is too high so it slowly charges the stray wiring capacitance plus the capacitance of the 'scope when the Jfet is turned off.
Try switching the 'scope probe to "divide by ten" which reduces its capacitance.

 

thanks! Forgot to model the capacitance.

I am using a jfet switch as part of a circuit which is used to attenuate large voltages and pass small ones at a particular frequency. I tried using a mosfet but the capacitance was too high for my needs.