JFET Design

Discussion in 'Homework Help' started by nathalie, Jan 9, 2011.

  1. nathalie

    Thread Starter New Member

    Jan 9, 2011
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    I've built a jfet voltage divider biasing scheme to output a constant current of 5mA and maximum voltage swing. On simulation, all is working correctly but when I built the circuit and tried to read the drain current, I cannot. What could be the problem?

    I've checked all the fuses of the multimeters, the power supply and I checked the transistor :S PLEASE HELP
     
  2. bertus

    Administrator

    Apr 5, 2008
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    Hello,

    Can you post the schematic?

    Bertus
     
  3. nathalie

    Thread Starter New Member

    Jan 9, 2011
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    ok my schematic is :
     
  4. bertus

    Administrator

    Apr 5, 2008
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    Hello,

    What BF244 are you using, the A B or C variant?

    The current can be regulated with a NEGATIVE Vgs (see diagram).
    I also attached the complete datasheet.

    [​IMG]

    Bertus
     
  5. nathalie

    Thread Starter New Member

    Jan 9, 2011
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    Thanks,
    I am using the BF 244B. I am using a Vgs of -3.2V maximum, while a minimum of -0.06V , which I calculated according to the pinch off equation of :

    Ids = Idss(1-Vgs/Vgs(off))^2

    Then I found the voltage Vg by solving the simultaneous equations of the input loop for the maximum and minimum values : Vgs = Vg-IdsRs

    I let Vd= Vdd/2 for maximum output swing and then according to the output loop equation : Vdd = IdsRd +Vd, I found Rd when Ids is 5mA

    The values of r1 and r2 where found using the equation Vg=Vdd(R2/(R1+R2)
     
  6. Adjuster

    Well-Known Member

    Dec 26, 2010
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    It would help if you could show in more detail how you got your results.

    From the resistor values you show in your diagram, the gate voltage looks likely to be too high. (About +15.6V, if the gate current were negligible, but in practice the voltage may be limited by gate conduction, since this is a JFET). This would imply a source voltage somewhere around 14V, if the Vgs was in the region you expect. As a result, I think that the Vds may be too low.

    What values does your simulation give for the voltages on the gate, source, and drain, with respect to 0V?

    As for the practical version, try checking over your circuit carefully for mistakes. Are you sure that you have connected the FET correctly? What about the other components?
     
  7. Adjuster

    Well-Known Member

    Dec 26, 2010
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    There seems to be a problem with the circuit values you have here.

    You state that Vg=Vdd*(R2/(R1+R2), which gives about 15.6V with your values.

    However you also have Vgs = Vg - Ids*Rs, so Vgs = 15.6V - 5mA*440ohm = 13.1V.

    That does not seem reasonable - it is positive and very big. Actually, a silicon JFET probably won't allow more than about +0.6V Vgs

    The data-sheet gives an absolute maximum forward gate current for this part of 10mA. Perhaps this has been exceeded?
     
    Last edited: Jan 9, 2011
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  8. Kermit2

    AAC Fanatic!

    Feb 5, 2010
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    nathalie likes this.
  9. nathalie

    Thread Starter New Member

    Jan 9, 2011
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    I've reworked the resistor values and simulations and ended up with :
     
  10. Jony130

    AAC Fanatic!

    Feb 17, 2009
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    PSpice for BF244B use Vt= - 2.29V, and Idss = 8.59mA


    Id = Idss*[1 - \frac{Vgs}{Vt}]^2

    So we want to know Vgs for Id=5mA

    Vgs = Vt*[1 -\sqr{ \frac{Id}{Idss}}] = -2.29V*[1 -\sqr{ \frac{5mA}{8.59mA}}] = - 0.542V

    Rs = 1V/5mA = 220Ω
    Rd = 9.5V/5mA = 1.8KΩ
    Voltage divider should provider voltage equal to:
    Vg = Id*Rs + Vgs = 0.558V
    Vcc/Vg = 20V/0.558V = 35.8
    R1/R2 +1 = 35.8

    So if R2 =10K then R1 = 34.8 * 10K = 348K = 330K

    So I think that you could try this diagram
    [​IMG]


    Rs = Vgs/Id = 0.542V/5mA = 100Ω
    Rd = 1.8KΩ
    Rg = 1MΩ
     
  11. Adjuster

    Well-Known Member

    Dec 26, 2010
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    OK, you have a low gate current now, but the transistor is still turned on pretty hard. Vds is only 0.71V.

    Normally we would expect the source voltage to be much lower than the drain, so that a large drain voltage swing would be possible, both positive and negative. This is difficult with such a high gate voltage Vg.

    Are you certain about your calculations for the Vg potential divider. I would expect Vg less than VDD/2.

    Actually Vg=0 is possible (See Jony's post), but you should probably use a potential divider if that's what your assignment asks for.
     
    Last edited: Jan 9, 2011
  12. Adjuster

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    One disadvantage of using Vg=0 is that the source voltage has to be much lower, so that source resistor also must be low, and the drain current is stabilised less.

    Were you not given some guide for the value of Rs?
     
  13. nathalie

    Thread Starter New Member

    Jan 9, 2011
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    In our assignment we have to use the voltage divider biasing scheme to obtain the maximum output voltage swing with a 5mA Ids ...How would I lower the Voltage Vg if I am considering the maximum and minimum values for Ids and Vgs(off) to ensure a good Q-point stability? Thanks :)
     
  14. Adjuster

    Well-Known Member

    Dec 26, 2010
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    There is a compromise between bias stability and available drain voltage. The drain current must be reasonably stable, but a practical circuit will need to be capable of a certain output voltage swing.

    It is even possible that the point of your exercise was to show that a design aimed for ideal bias stability would have very limited output.

    I think it more likely though that there has been some error, either in your working or in the question itself. Is there any chance you have copied the question down incorrectly?

    What requirements were you asked to meet in the exercise?
     
  15. nathalie

    Thread Starter New Member

    Jan 9, 2011
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    We require a maximum output swing with a 5mA output current and Q-point stability. I thought we should use the voltage divider scheme as it offers the maximum output Q-point stability
     
  16. Adjuster

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    Dec 26, 2010
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    OK let's try this just once more: HOW stable is the drain current required to be?

    5mA +/-20%? 5mA+/-2mA, or what?

    Perfection is not possible, even if you took the gate voltage Vg up to Vdd, at which point there would be very little possible swing at the drain.

    Can you state the original question, exactly.
     
  17. nathalie

    Thread Starter New Member

    Jan 9, 2011
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    the original question was design a transistor biasing circuit using an FET to achieve a quiescent output current of 5mA.The positioning of the operating point should allow for maximum output signal swing at the output and the biasing circuit should provide automatic Q-point stability. Simulate and construct your design.
     
  18. Adjuster

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    I was going to say that this was an open-ended question, but I note from your earlier post that you say:
    Can you show how you did that to get such a high value for Vb ?
     
  19. nathalie

    Thread Starter New Member

    Jan 9, 2011
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    I let Idsmin = 4.5mA and using the equation Ids=Idssmin(1-Vgs/Vgs(off))^2 I found Vgs min

    then I let Idsmax = 5.4 and using the previous equation i found vgs max.

    The solutions are then inserted in the equation Vgs = Vg-IdsRs, which resulted into 2 equations that can be solved simultaneously
     
  20. Adjuster

    Well-Known Member

    Dec 26, 2010
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    Does this method ignore some changes in Vgs because of the error in Ids? This could over-estimate the Ids variation, don't suppose by much though. You have required Ids to be within about 10% of its target value. This requires a high source resistor voltage, to sufficiently dilute the uncertainty caused by the spread on Vgs.

    Personally I would aim for lower Ids accuracy, perhaps 25%, but you must do what your assignment requires. I'm not a teacher, and don't want to mislead you. The exercise may even have been designed to illustrate the difficulties of biassing devices with wide tolerances.

    I would be interested to know what was really expected, if ever you find out.
     
    Last edited: Jan 10, 2011
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