Hi everyone,

From the figure, it's shown that JFET is configured as voltage-controlled resistor. For a JFET to be effective as a linearly responding resistor, why it's important to limit VDS to a value that is small compared with VGS,off and to keep VGS below VGS,off ? If VGS is below VGS,off , isn't the JFET would be in off condition? Thanks for anyone who can answer me...

 

Have you see this papers
http://users.ece.gatech.edu/~lanterma/sdiy/datasheets/transistors/vcr2n4n7n.pdf
http://users.ece.gatech.edu/~lanterma/sdiy/datasheets/transistors/vishay_fet_cvr_an.pdf
http://freespace.virgin.net/ljmayes.mal/comp/vcr.htm

 

Thanks for the papers, I have just read it. I still don't understand why VGS must be keep below VGS,off in order for the JFET to operate as a voltage-controlled resistor as mentioned in the book I'm reading. A JFET would start operating at VGS=0V and below which is negative voltage until a certain value that is low enough to turn it off. If VGS is less than VGS,off, wouldn't the JFET in off condition and coudn't operate???

 

If the FET turns off with a VGS of -5V then with a VGS of 0V to about -4.5V it will work as a variable resistor and its VGS will be less than VGS-off.

 

Hi everyone,

From the figure, it's shown that JFET is configured as voltage-controlled resistor. For a JFET to be effective as a linearly responding resistor, why it's important to limit VDS to a value that is small compared with VGS,off and to keep VGS below VGS,off ? If VGS is below VGS,off , isn't the JFET would be in off condition? Thanks for anyone who can answer me...

You need to spend some time reading up on the behavior of JFET transistors. It sounds like you have not yet figured out what voltage range, when applied to the gate, places the JFET into the linear operational mode.

hgmjr

 

Lkgan, you have some erroneous information. Vgs must be between Vgs(off) and 0V.

 

If the FET turns off with a VGS of -5V then with a VGS of 0V to about -4.5V it will work as a variable resistor and its VGS will be less than VGS-off.

|Vgs| will be less than |Vgs(off)|, but -4.5V is greater than -5V.

 

Vd has to be small because the curves become progressively more nonlinear the farther they get from zero volts. See the highlighted region in the graph below (courtesy of Vishay).

 

-5V is more negative than -4.5V.
Therefore -4.5V is less than -5V.

 

http://www.mathleague.com/help/posandneg/posandneg.htm

Scroll down to The Number Line.

 

You need to spend some time reading up on the behavior of JFET transistors. It sounds like you have not yet figured out what voltage range, when applied to the gate, places the JFET into the linear operational mode.

hgmjr

I am reading the behavior of JFET and know that the operational mode is between VGS= 0V to some negative value for the JFET to be off, which is VGS,off. The thing that I don't understand when I came across while reading was why need to keep VGS below VGS,off ? As Ron H have mentioned, it might be erroneous from the book. I just need confirmation with that as I find it's an error too....

 

Vd has to be small because the curves become progressively more nonlinear the farther they get from zero volts. See the highlighted region in the graph below (courtesy of Vishay).

I got it. When JFET is operating at linear mode, VDS is very small, that's why VD have to be small. But the question is, why it's important to limit VDS to a value that is small compared with VGS,off ? I have got no idea about this statement from the book.

 

Well, the smaller the Vds is, the more linear resistor you get.

 

The Number Line favours positive voltages.
-5V is more bias voltage than -4.5V.
Therefore -5V is also more bias voltage than 0V.
"More" is "greater than".