J-K master slave flip flop

Discussion in 'Homework Help' started by circuit2000, May 4, 2007.

  1. circuit2000

    Thread Starter Active Member

    Jul 6, 2006
    33
    0
    Does an edge triggered J-K master slave flip flop exist? In a clocked J-K master slave flip flop, the master may be positive edge triggered and the slave may be negative edge triggered or vice versa. Can this flip flop be called an edge triggered J-K master slave flip flop?If so,is it positive edge triggered or negative edge triggered?Then what about the truth table? In the column of clock in the truth table, should a pulse symbol or positive edge or negative edge be drawn?
     
  2. Ron H

    AAC Fanatic!

    Apr 14, 2005
    7,050
    656
    An edge-triggered FF consists of two cascaded latches. The state of the first (master) is receptive to data change, and follows the data, during the first portion of the clock cycle. The second (slave) does not "see" the master during this time. When that portion of the cycle ends, the state of the master at that instant is latched. Simultaneously, the second (slave) is opened and "sees" the state of the master. The output, of course, will then change if the new state of the master is different from the previous state of the slave. This edge is the trigger edge.
    When the second portion of the clock cycle ends, the slave output can no longer "see" the state of the master, and of, course, its state does not change. The master again becomes receptive to data.
    I used the word "portion" instead of "half" because there is no requirement that the clock have a 50% duty cycle.
     
Loading...