Isd/Vsg of a PMOS transistor

Discussion in 'General Electronics Chat' started by Yarrow, Sep 12, 2007.

  1. Yarrow

    Thread Starter Member

    Sep 18, 2006
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    Hey, I am having a hard time measuring the Isd/Vsg of a PMOS transistor. I did a NMOS and measured Ids/Vgs by using schematics like shown in the attachment, and now I am supposed to modify the schematic to measure Isd/Vsg og a PMOS transistor. I am quite confused about how "holes" and electrons travle through the circuit, so I cant figure out how to configure the circuit. If you look at the attachment you clearly see what I am missing. If someone could spare a couple of minutes to draw a schematic for PMOS Isd/Vsg measurments and a couple key words explaining the process, I would really grateful!! Tnx in andvance
     
  2. beenthere

    Retired Moderator

    Apr 20, 2004
    15,815
    282
    Your "schematic" is pretty sparse. If you take the trouble to draw the device properly, and to enter some test values, we might be able to help out by identifying any problems with the setup.
     
  3. Yarrow

    Thread Starter Member

    Sep 18, 2006
    23
    0
    Ok, I will try to explain what it is that I am doing. I just want to say that I am measuring, not simulating using software. What I have done for the NMOS transistor is that I have measured the Ids as a function of Vgs. This has been done in a lab, using power supply and multimeter. The power supply and multimeter are connected to the computer, and I use MATLAB to run a script sweeping the Vgs from 0V-5V. I set Vdd to 5V aswell. The result I got was as it should be. The problem is, I was supposed to do the same for the PMOS.

    Now what my problem is, is that I dont know how to configure the measurment setup for a PMOS transistor to show a graph of Isd as a function of Vsg. Where should I put the (A), and how can I rout the wires so that my graph is correct?

    I have attached a couple of files.
    1: NMOS measurment setup
    2: Ids as a function of Vgs for a NMOS transistor

    I have hardly done any measuring in a lab before, I have for the most done modelling . And when I modelled the graphs were identical in form for both PMOS and NMOS, only the axis were changed from Ids/Vgs for NMOS to Isd/Vsg for PMOS. This is possible when measuring aswell, right? That measurment setup for PMOS is what I am after, though I dont know how to configure the measurment setup as mentioned.


    You might notice that Vt (Threshold voltage) for the NMOS is about 1.7V. I am also abit uncertain about that, what do you think, does it sound normal? I am using MC14007UB - CMOS Transistor Package.
     
  4. Eduard Munteanu

    Active Member

    Sep 1, 2007
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    Yarrow, try looking on real-world CMOS transistor datasheets. As with other active devices, they sometimes include test and measurement schematics. You should also try JEDEC's website and see in what conditions those measurements have to be made.
     
  5. Yarrow

    Thread Starter Member

    Sep 18, 2006
    23
    0
    I did look in the datasheet for the transistor pack, but nothing on the PMOS transistor, only NMOS. Anyways I just did a Cadence simulation on a PMOS transistor and I got a graf that is "invertet" compared to NMOS. The attachment shows Id/Vg of a PMOS. Now is this Ids/Vgs or Isd/Vsg?
     
  6. beenthere

    Retired Moderator

    Apr 20, 2004
    15,815
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    Here is the Wikipedia article that has some possibly useful references, plus the accepted way to draw the schematic symbols for the transistors - http://en.wikipedia.org/wiki/MOSFET.
     
  7. Yarrow

    Thread Starter Member

    Sep 18, 2006
    23
    0
    beenthere, that article does not say anything about (current) measurment setup. That is what I am looking for. It really should be a basic thing, its just that I have forgot basic electronics. :S

    I posted a "NMOS measurment setup" attachment, so I am looking for a "PMOS measurment setup" instead.
     
  8. Distort10n

    Active Member

    Dec 25, 2006
    429
    1
    I am curious why the set up would change. The only difference with the PMOS is that the gate must be more negative than the drain or source for current to flow in the channel. Polarity and thresholds aside, why couldn't it be the same?
     
  9. Yarrow

    Thread Starter Member

    Sep 18, 2006
    23
    0
    knightofsolamnus, if the setup remains the same, I get a graph like "PMOS_Id_graph_Cadence.JPG" attached in my third post. I am not sure if this is Ids/Vgs or Isd/Vsg. So the setup i am after gives out a graph that is identical (in form) to the NMOS Ids/Vgs graph. Notice that I want Isd/Vsg (PMOS), and not Isd/Vgs (NMOS). I think the change Ids -> Isd and Vgs -> Vsg is a main reason for the graphs remaining the same for PMOS and NMOS. But to accomplis that, I have to change the measuring setup.
     
  10. Yarrow

    Thread Starter Member

    Sep 18, 2006
    23
    0
    Hey, tnx for all the help. I found out what the setup should be when measuring the Isd/Vsg for a PMOS. audioguru at electronics-lab.com managed to find what I was after. So I thaught I could post the result.
     
  11. Eduard Munteanu

    Active Member

    Sep 1, 2007
    86
    0
    Yarrow, this circuit is what knightofsolamnus was suggesting.
     
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