Is there a paradox here?

Discussion in 'Homework Help' started by anhnha, Oct 6, 2013.

  1. anhnha

    Thread Starter Active Member

    Apr 19, 2012
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    Hi,
    Is there a paradox in the circuit below.
    Assuming that both transistors are in saturation.
    • M2 is PMOS and its VSG is constant, therefore, Id = constant
    • M1 is NMOS and assuming that Vin varies with time, so Id also changes with time.
    If so, is there a conflict here?
    [​IMG]
     
  2. LvW

    Active Member

    Jun 13, 2013
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    No - there is no "paradox".
    ID2 of M2 is NOT constant, because it depends not only on VSG2 but also on VDS2 (remember the slope of the ID=f(VDS) set of curves).
    And VDS2 changes due to the varying value of ID1=ID2=ID.
     
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  3. anhnha

    Thread Starter Active Member

    Apr 19, 2012
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    How about if we ignore channel length modulation here? Then Id depends only on Vgs not Vds.
     
  4. LvW

    Active Member

    Jun 13, 2013
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    Yes - a series connection of two IDEAL current sources could be a problem.
    Fortunately, there are no ideal devices.
     
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  5. WBahn

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    Mar 31, 2012
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    +1

    As noted in several other threads recently. If you use idealized models, then you can easily construct circuits that have no solution. When that is the case, you need to introduce more realistic models.
     
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  6. anhnha

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    Apr 19, 2012
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    I usually use ideal models at first because it is more easier for me to understand. To me it seemed that it should be roughly correct for ideal model and to get more accurate results then using realistic models. Didn't think about the "no solution" in ideal models.
     
  7. WBahn

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    Mar 31, 2012
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    In general, an ideal model (or any model, for that matter) is a simplification that makes it so that constructs (circuits, in our case) that rely on what has been simplfied away cannot give useful answers (or even answers at all) for the simple reason that what those circuits rely on has been simplified away and, hence, the construct is fundamentally incompatible with the model.

    This is a case in point. The ideal model simplifies things by saying that the current in each transistor is a function of the Vgs. Okay, that's fine as long as you only use it is circuits in which the current being a sole function of Vgs is not incompatible with the circuit constraints. But in the circuit you showed, the circuit also requires that the current in each of the two transistors be the same, since they are in series. Yet each transistor has a separate Vgs, meaning that the system is overdefined -- you have more control parameters than you have controllable variables (two Vgs values but only one Ids variable). So you need models that introduce a way to resolve the conflict and adding non-infinite output impedance does that. Since the Ids of each transistor is now a function of both Vgs and Vds, you can set the two Vgs values to whatever you want, but the model now gives a means for the circuit to adjust the Vds values such that the Ids of both transistors is the same.
     
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  8. LvW

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    Jun 13, 2013
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    In many cases, I do the same. And, I think, this is a good approach - as long as
    * you are aware that the results are valid for this ideal case only, and
    * you know (or have a good feeling, at least) under which conditions the
    assumed simplifications do not apply anymore.

    I think, in particular the last point is rather challenging as it requires a deep understanding of circuit design and system theory.

    As a simple example - take an opamp wired as unity gain amplifier.
    * At first, keep in your mind that the frequency range with unity gain is limited under real conditions. But this will be no problem if the circuit is used for frequencies in the lower kHz range only.
    * Secondly, in practice the whole circuit might not work at all in case you select an opamp that is not unity-gain stable.
    ___________
    Summary: Working with simplifications (ideal models) can be dangerous for beginners and can be recommended (as a first design step!) if you really know what you are doing.
     
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  9. studiot

    AAC Fanatic!

    Nov 9, 2007
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    You should also take note that you have Vout so there is an alternative current path through the load to take care of variations of Vin causing variations in the lower FET drain current.
     
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  10. WBahn

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    If there is a load, which there isn't in the circuit as given and which there may or may not be in practice (and, if there is, it may be too high of an impedance to take the difference).

    But, if there is a load and it has sufficiently low impedance (and the transistors have sufficiently high output impedance), then this circuit acts as a transconductance amplifier, which can be very useful.
     
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  11. studiot

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    Agreed, no load is shown, but no output impedance is shown for whatever supplies Vin either.

    So what good is an isolated cicuit element that does not work at all well by itself, without the rest of the circuit?

    It's like complaining that an ohmmeter draws no current without a test resistor connected.
     
  12. anhnha

    Thread Starter Active Member

    Apr 19, 2012
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    I thought about the load but then I assumed that if there is a load there, we will usually make it very large and thus it has no effect to the previous stage.
    Is this right?
    I can't figure out what it is. In this case, can I model it by an voltage controlled current source in series with Zout and RL?
    Zout is very large and RL is small enough therefore, we ignore RL.
    The output current Iout will be directly proportional with Vin. Is my understand correct?
     
  13. THE_RB

    AAC Fanatic!

    Feb 11, 2008
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    Nope, Id depends on Vgs AND on whatever is connected to d or s.

    A better way to evaluate is to consider that "Rdson depends on Vgs".

    So a fixed Vgs sets a fixed "resistance" between d and s, and then like any resistor the current depends on all the factors in the external circuit.
     
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  14. anhnha

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    Apr 19, 2012
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    Well, that solved all problem!
     
  15. WBahn

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    That's the case in the triode region, but not on the saturation region in which the Ids is nominally indepdent of Vds (and this is the basic model that the OP is talking about, because as soon as their model includes even output resistance the "paradox" goes away).
     
  16. anhnha

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    Apr 19, 2012
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    In the triode region, the resistance between D and S, Rdson, is almost a function of Vgs, Vds can be ignored.
    And in the saturation, can we consider that there is a resistance between D and S with its value depends only on Vgs?
    Can I call it is "voltage controlled resistance"? As a result if I replace the bottom transistor by this resistor, the problem seems to go a way.
     
  17. WBahn

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    It's the other way around.

    In the triode region, for a given value of Vgs, the current through the device, Ids, is a function of Vds. For Vds sufficiently low compared to Vgs (in rough terms), this ratio of Vds to Ids is roughly constant. This ratio is Rds and hence, yes, Rds is a function of Vgs alone (roughly). But that does not mean that Vds can be ignored. Vds may not influence the value of Rds, but it as soon as we even talk about there being an Rds we are saying that Vds is very much a factor in the current -- that's what a resistor means!

    In the saturation region, we are NOT saying that we have a resistance between D and S, we are saying that (to first order) we have a voltage controlled current source in which Ids is a function of Vgs and IS indepedent of Vds, provided Vds is sufficiently high relative to Vgs. In the basic model, the effective inremental resistance between D and S is infinite, meaning that a change in Vds has virtually no effect on Ids.
     
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  18. LvW

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    Jun 13, 2013
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    In the context, as discussed above, it is important to point to the following fact:
    The definition for the saturation region of FET`s does NOT correspond to the definition of the saturation region for BJT`s. This has historical reasons. In both cases, saturation means not the same.
    This unfortunate discreapancy of terms sometimes creates misunderstandings.
     
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