hello all,
Before going to test my three phase inverter with a 400VDC...... i want to test it with 9VDC. The gate pulses are of 12VDC magnitude coming out from a IR2110 (high & low side driver). The pulse sequence fashion is correct in oscilloscope....... but both the mosfets in a leg are conducting simultaneously.....
is there any rule to have vgs < Vds?
see the attachment
Before going to test my three phase inverter with a 400VDC...... i want to test it with 9VDC. The gate pulses are of 12VDC magnitude coming out from a IR2110 (high & low side driver). The pulse sequence fashion is correct in oscilloscope....... but both the mosfets in a leg are conducting simultaneously.....
is there any rule to have vgs < Vds?
see the attachment
Attachments
-
62.4 KB Views: 45