I want to model a CMOS inverter as
output = NOT (input) after 10us
in Spice. I used LTspice for that and I am getting that,

(ckt1.jpg, please see attachments)

but I am expecting that,

(ckt2.jpg, please see attachments)
Please help me to create a proper circuit that shows the delay between input and output waveforms clearly.
If possible please send me a working code/file e.t.c.

Thanks......

 

Put R1 between C1 and node Out.

 

Thanks a lot for replying but I still not getting the result, on putting R1 between C1 and out I am getting this,

[ckt3.jpg(please see attachments)]

 

The output is between C1 and R1.