Inverter questions

Discussion in 'Homework Help' started by electronicsbeginner12, Apr 27, 2015.

  1. electronicsbeginner12

    Thread Starter New Member

    Dec 14, 2014
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    Hi. I have some basic questions on inverters. If the logic symbol has a bubble on the output, that means the output is opposite of the input. So a high input will result in a low output and a low input will result in a high output. Is this the same if the bubble in located on the input side of the logic symbol instead of the output side? Also, what if there is a bubble on both the input and output side of the inverter logic symbol? Thanks!
     
  2. MrChips

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    Oct 2, 2009
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    The bubble means a NOT gate, i.e. an inverter.

    The proper interpretation of a bubble on an input means that the signal is ACTIVE-LOW, i.e. a LOW input activates the function. If the input function is edge triggered then a HIGH-to-LOW transition activates the function.

    A bubble on an output pin means that the output signal is ACTIVE-LOW, i.e. a LOW output means the function has been activated.
     
  3. Papabravo

    Expert

    Feb 24, 2006
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    The bubbles allow you express the DeMorgan equivalent of a logic function. For Example:
    A LOW .AND. a LOW is a LOW (bubbles on both inputs and the output) is exactly the same logic function as a HIGH .OR. a HIGH is a HIGH (no bubbles anywhere). Repeat this mantra over and over until the meaning is clear.
     
  4. WBahn

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    Mar 31, 2012
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    The simplest and cleanest way to understand the bubble is that it is nothing more than a graphical shorthand for an inverter. Where ever you see it, you can remove the bubble from the symbol and insert an inverter in the signal line at that location and you will have changed nothing from a logical standpoint. That works backwards, too. You can remove an inverter from a signal line by replacing it with a bubble applied either to the output driving the inverter's input or to all of the inputs driven by the inverter's output (you can't do both).

    So look at the symbol for a NAND gate. It's an AND gate with a bubble on the output. You can remove the bubble and have an AND gate followed by a NOT gate. The logic is the same -- NAND is short for NOT- AND.

    With a bit of practice you can do a lot of logic minimization right on the schematic using what is called "bubble logic".
     
  5. MrChips

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    When there is a signal that is ACTIVE-LOW we draw a bar over the label. The bar becomes part of the label and reminds us that the signal is ACTIVE-LOW. We call this NEGATIVE LOGIC.

    There are two ways of drawing a NOT gate as shown in U2A and U2B. One of the two symbols is preferred depending to whether the signal is ACTIVE-HIGH or ACTIVE-LOW.

    Gate U4A is implemented with an AND gate. The OR gate shown is the proper way to illustrate this function because the logic function is an OR function.

    [​IMG]
     
  6. MrChips

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    Here is another example of "bubble logic":

    [​IMG]

    Here you see how both versions of the NOT gate are used appropriately.

    Sometimes we look at bubbles as "beads on a wire". You can slide a bead along the wire if it helps you better to visualize the logic. Two beads on the same wire will cancel out. The bead on U2A cancels that on the lower input of U4A.

    If you slide the bead from the output pin of U4A above, remember that the same bead must propagate to both branches shown.
     
  7. electronicsbeginner12

    Thread Starter New Member

    Dec 14, 2014
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    Thanks for all the responses so far. I want to make sure I'm understanding the inverter (NOT circuit) first. So if the bubble is located on the output, a HIGH input will cause a LOW output. This is called active LOW output, right? If the input goes LOW, then output goes HIGH? If the bubble is located on the input side, a LOW input will cause a HIGH output which is called active LOW input? If I'm correct so far, then was does it matter where the bubble is placed since the inverter will invert the signal from input to output anyway?
     
  8. Papabravo

    Expert

    Feb 24, 2006
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    You can place the bubble where you want to and it won't change the logic. The nearly universal convention in logic drawings is to place it on the output of an inverter. With logic gates, it is often an aid to understanding to draw it in the DeMorgan equivalent, eg. drawing an AND gate with bubbles on the two inputs and the output as an OR gate. When you see it you say to yourself "a LOW or a LOW is a LOW" and you think AND gate, a 74LS08 or whatever your favorite AND gate is.
     
  9. MrChips

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    SN74LS04 and CD4049 are NOT gates or inverters.
    LOW input gives HIGH output. HIGH input gives LOW output.
    There are two ways to draw a NOT gate. Either way, it is still the same NOT gate.

    The difference is in how the schematic is drawn. Since you have a choice of how to draw the NOT gate, one of the two ways will give the observer a clearer understanding of the logic function of the associated gates and signals.

    The one simple analogy I can think of is the way you label a door handle, PUSH or PULL.
    It would be ridiculous to have it labeled backwards, wouldn't it?
     
  10. electronicsbeginner12

    Thread Starter New Member

    Dec 14, 2014
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    Thanks for the responses. I was initially confused regarding the placement of the bubble and unsure if that changed the logic of the gate. Now its more clear to me knowing that the logic doesn't change, but the placement of the bubble is there to emphasis exactly what is going on in the circuit.So a NAND gate is equivalent to an negative OR gate and an NOR gate is equivalent to negative AND gate where the truth tables are exactly identical. Am I getting this?
     
  11. WBahn

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    Yes. This is called logical duality. This is also why a 7400 NAND gate is properly called a Positive Logic NAND gate. It is only a NAND function if you define a high voltage to be a logic True and a low voltage to be a logic False. But these are arbitrary definitions and the circuitry on the chip doesn't care. If we call a low voltage a logic True and a high voltage a logic High then that exact same circuit is now an NOR gate.
     
  12. MrAl

    Well-Known Member

    Jun 17, 2014
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    Hi,

    As you are probably finding out now, you have to be a little careful what you call "Active" low or high, and that is because of the interpretation of the gate, as to it's function in the circuit...not to it's function as it is sold in the marketplace.

    For example, if we have a two input NAND gate (bubble on output, none on the two inputs) and it gets two signals from two other places in the circuit, the output could be labeled NOT READ ENABLE or it could be labeled just READ ENABLE, because it depends on the designer how they wanted to use the NAND gate. If it is labeled NOT READ ENABLE (ie READ ENABLE with a bar over the text) then that means that the signal does what it says it does when the two inputs BOTH go high, but if it is labeled READ ENABLE then that means that it does what it says it does when EITHER of the inputs goes low. So there is no real correlation between the bubbles and the NOT or non NOT labeling, it's all in the intended functional design.
    In some cases but not all the drafter will replace the regular NAND gate symbol with a negative logic NOR gate symbol (two inputs with bubbles but the output has none and it is drawn like an OR gate instead when really it is sold as a NAND gate like the 74LS00 TTL gate). They dont always do that however and sometimes stick with the original drawing (like a AND gate with bubble on output) to match the part specification as it is sold in the marketplace, so the nomenclature might not match the bubbles in every schematic you find.
     
    Last edited: May 2, 2015
  13. electronicsbeginner12

    Thread Starter New Member

    Dec 14, 2014
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    Thank you everybody for clarifying.
     
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