inverter implied with nmos driver and pmos diode load.

Discussion in 'Homework Help' started by vustudent, Oct 16, 2010.

  1. vustudent

    Thread Starter Active Member

    Mar 11, 2009
    38
    0
    Here is a inverter design of a nmos driver with a pmos diode connected load.
    Vdd is 1.2V, input is DC biased at 500mV with 50m AC small signal.

    [​IMG]

    the pmos attributes are set as the follow:
    vto=-0.42
    uo=90
    tox=3.2n
    gamma=0.24
    kp=0.933m

    I would want to fix kp to this value, since i would then have an output resistance of 1/gm , which would gives me ~25M Hz bandwidth with a 1pf load.

    The gain equation for this inverter is -gm(nmos) * Req(pmos)
    = -gm(nmos)/gm(pmos)

    which boils down to [​IMG]

    To get a gain of -2
    I set Kn = 4Kp
    nmos attributes:
    vto=0.39
    uo=518
    tox=3.2n
    gamma=0.28
    kp= 0.933m

    [​IMG]

    The output is biased at 560mV and i got a gain ~-2.

    Then I tried a gain of -1
    set kp=kn

    and got I below:

    [​IMG]
    The output in green is now biased at 670mV with a gain of -1

    My question is how is the biased output voltage determined, and how do I control it?
     
    Last edited: Oct 16, 2010
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