By tying the charge to the PWM it gives the problem you just mentioned. The way my circuit is, the charge is actually taking place longer than one clock period. This way the caps are sure to be fully charged.
Also having the flip-flop plus 'and' gate was the only way I found of having both alternating discharges and full control over the other elements I needed. By other I mean the high and low cap voltage comparators.
I read an App Note on the UC3842/43. It shows that the osc pulse goes low as the PWM output goes high. I'll add the app note to this post. Page 11 shows the timing. It also shows using a 555 for the clock, instead of a RC .
Also having the flip-flop plus 'and' gate was the only way I found of having both alternating discharges and full control over the other elements I needed. By other I mean the high and low cap voltage comparators.
I read an App Note on the UC3842/43. It shows that the osc pulse goes low as the PWM output goes high. I'll add the app note to this post. Page 11 shows the timing. It also shows using a 555 for the clock, instead of a RC .
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