Inverted input? (not inverting)

Thread Starter

shortbus

Joined Sep 30, 2009
10,045
Yes the power resistors are in the 100V supply. Between the filter cap and the charge mosfet.

The PWM allows the duty cycle of the frequency to be controlled, in effect controlling the amperage. There are no inductors involved. The discharge is a spark gap in a dielectric oil.

As the discharge starts, the voltage in the gap ionizes a path in the oil. This then allows the current to start to flow, dropping the voltage to about a third of the open voltage. This current creates a temperature of ~3000 degrees F melting a small crater of metal out. The PWM then shuts down the flow of electricity, and the oil flows in and washes the gap clean and the process starts again.

This process, EDM has been around since right after WW2.The first ones were RC oscillator circuits. Using high value resistors and caps with the gap resistance controlling discharge. They worked but didn't give any real control of the machined finish.

The first pulsed machines used a rotating disc with contacts on it mechanically controlling the frequency and duty cycle. They didn't work very good. This was late 50's early 60s.

Then came the style I'm trying to replicate. Smaller cap values and adjustable frequency and duty cycle. But in my logic circuit I'm adding the isopulse to control the gap voltage better, to give a better finish to the machined part.

There is also a voltage comparator/servo that keeps the electrode at the correct distance as the metal is removed. That part of the machine is done, just need to work out this spark generator circuit now.
 

Ron H

Joined Apr 14, 2005
7,063
Are you dumping the capacitors into a high voltage transformer? Maybe you already mentioned that?
I would be surprised if you could break down an oil film with 100 volts.
 

Thread Starter

shortbus

Joined Sep 30, 2009
10,045
Ron, no it is just the caps. The gap is only .001 - .002 inches. They actually do it with less than 100V in some machines. But ~100VDC is the average. On my old computer, may it rest in peace, I had a chart of milli Joules each different cap would give.

Here is a PDF of a commercially built one. Though it is more powerful than what I'm trying to do.
 

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Ron H

Joined Apr 14, 2005
7,063
I ran a simulation of your circuit. It looks like it should work.
Can you run LTspice? If so, I will post the .asc file.
If not, post a timing diagram of the inputs to the two half-bridge drivers, and i'll try to run my sim with your timing, and post the results.
 

Thread Starter

shortbus

Joined Sep 30, 2009
10,045
Thank you very much! I have tried to use LTspice but get lost. Many of the parts I need aren't available and I don't understand making them. I can build from a schematic, but this is my first attempt at a design form scratch. You guys here have been a great help, and a big inspiration to me.

I'll draw up a timing diagram.
 

Ron H

Joined Apr 14, 2005
7,063
Thank you very much! I have tried to use LTspice but get lost. Many of the parts I need aren't available and I don't understand making them. I can build from a schematic, but this is my first attempt at a design form scratch. You guys here have been a great help, and a big inspiration to me.

I'll draw up a timing diagram.
Be sure you include the time scale.
 

Thread Starter

shortbus

Joined Sep 30, 2009
10,045
OK two new attachments to show. This is good for me in two ways:) I'm first getting help that I both need and appreciate, and may even finish the project before I kick the bucket.:p And second, I'm getting stuff that was drawn sloppily on scraps of paper drawn in a better way.

The one attachment is the logic for one bank of caps. And the connections to the second bank, which will be the same.

The other attachment is the timing chart. Didn't know the correct way to show a PWM, so just used a dashed line for the high edge.

Again thank you, Ron and Praondevou, for your help!

Edit: to all seeing this, the logic schematic shown is wrong!!! The revised schematic is in post #34
 

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praondevou

Joined Jul 9, 2011
2,942
What is the 74HC04 for? Has the "charge" driver inverted input logic?

The charge is not controllable by PWM. That is correct I assume?

Can you draw up the comparator resistor divider network too ( or maybe you did and I didn't see it ) ?
 

Ron H

Joined Apr 14, 2005
7,063
OK two new attachments to show. This is good for me in two ways:) I'm first getting help that I both need and appreciate, and may even finish the project before I kick the bucket.:p And second, I'm getting stuff that was drawn sloppily on scraps of paper drawn in a better way.

The one attachment is the logic for one bank of caps. And the connections to the second bank, which will be the same.

The other attachment is the timing chart. Didn't know the correct way to show a PWM, so just used a dashed line for the high edge.

Again thank you, Ron and Praondevou, for your help!
Your HC74 is connected as a toggle (divide-by-2) flip-flop. Your Q and /Q outputs will be complementary, 50% duty cycles square waves at half the clock frequency, not pulses as shown on the diagram.
Also - where do the outputs "to charge gate A" and "to charge gate B" go?
 

Thread Starter

shortbus

Joined Sep 30, 2009
10,045
What is the 74HC04 for? Has the "charge" driver inverted input logic?

The charge is not controllable by PWM. That is correct I assume?

Can you draw up the comparator resistor divider network too ( or maybe you did and I didn't see it ) ?
AH-HA, this is a good reason to post this stuff before building.:) The 74hc04 should have been connected to the Q of the 74hc74.

The 74hc04 would then turn on the charge fet when the discharge fet for that capacitor bank is off.

Correct, the charge is not PWMed.

Will do on the resistor dividers.
 

Thread Starter

shortbus

Joined Sep 30, 2009
10,045
Your HC74 is connected as a toggle (divide-by-2) flip-flop. Your Q and /Q outputs will be complementary, 50% duty cycles square waves at half the clock frequency, not pulses as shown on the diagram.
Also - where do the outputs "to charge gate A" and "to charge gate B" go?

This part of the circuit was my sticking point for a long time. How to make duplicate but alternating signals. I finally found the answer in a post by MikeMl on the ETO forum. A flip-flop and two "and" gates.

By using the 74hc74 Q and /Q to "and" gate 74hc21. The on going PWM signal (plus the comparator outputs) will alternate from one capacitor bank to the other. This will make the total frequency of the in effect stay the same.

The outputs go to control the fet gates on the capacitor banks.

In my answer to Praondevou, I told him I made a mistake on my logic schematic. I'll correct that. And make a block diagram of the complete circuit.
 

Ron H

Joined Apr 14, 2005
7,063
All I need to see is a timing diagram of the logic signals going into the two half-bridge drivers. I don't care how you develop those signals, because I'm not simulating that part.
 

praondevou

Joined Jul 9, 2011
2,942
Just to make sure I get this right: (see picture below)

Q1 has a variable ON/OFF time.
Q2, Q3 and Q4 have fixed ON/OFF time. Q3 and Q4 are just inverted , due to HIN//LIN of U2 being tied together.
The cap bank is charged to a voltage that changes with ON time of Q1.

If these assumptions are correct then HIN and /LIN of U1 cannot be connected together.

Please describe what each transistor is supposed to do when:
- cap bank is lower than 10V
- between 10V and 90V
- higher than 90V
Right now it looks like "discharge gate A" (from the logic circuit) will be low whenever the cap voltage is lower than 90V. It is blocked either directly via the 10V comparator or via the 375 latch when lower than 90V. Maybe you inverted the upper comparator?

The cap B frequency is divided by 4 while the cap A frequency is only divided by 2. Is that correct?

I'm not familiar with this device you want to build. That's why a correct timing diagram for the 4 MOSFETs of each Cap bank is needed.

 

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Thread Starter

shortbus

Joined Sep 30, 2009
10,045
Just to make sure I get this right: (see picture below)

Q1 has a variable ON/OFF time.
Q2, Q3 and Q4 have fixed ON/OFF time. Q3 and Q4 are just inverted , due to HIN//LIN of U2 being tied together.
The cap bank is charged to a voltage that changes with ON time of Q1.

If these assumptions are correct then HIN and /LIN of U1 cannot be connected together.

Please describe what each transistor is supposed to do when:
- cap bank is lower than 10V
- between 10V and 90V
- higher than 90V
Right now it looks like "discharge gate A" (from the logic circuit) will be low whenever the cap voltage is lower than 90V. It is blocked either directly via the 10V comparator or via the 375 latch when lower than 90V. Maybe you inverted the upper comparator?

The cap B frequency is divided by 4 while the cap A frequency is only divided by 2. Is that correct?

I'm not familiar with this device you want to build. That's why a correct timing diagram for the 4 MOSFETs of each Cap bank is needed.

@Praondevou, no Q1 is fixed. Q3 is the variable timing. But since reading your words, the way this is drawn won't work.:( I have to do some rethinking here.

The frequency of the SG3525 is divided by two, but because each cap bank discharges alternately, the frequency stays the same as the SG3525 output.

But let me go back to part of the original question. Will using the low side fet's Q2, Q4, work to recharge the boot caps?

Some would see this as a failure, but its a learning experience to me.
 
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praondevou

Joined Jul 9, 2011
2,942
@Praondevou, no Q1 is fixed. Q3 is the variable timing. But since reading your words, the way this is drawn won't work.:( I have to do some rethinking here.

But let me go back to part of the original question. Will using the low side fet's Q2, Q4, work to recharge the boot caps?
Yes, upper and lower transistors form two common half-bridges.

Ok, if Q3 and Q4 are just having opposite gate signals you can tie HIN and /LIN of U2 together. I don't see a problem with that. Makes a variable ON/OFF time for Q3 and Q4. (Within limits).

What about the Comparator logic?
 

Thread Starter

shortbus

Joined Sep 30, 2009
10,045
What I really want to see is circled in the attachment. As I said in my last post,

PS include time scale.
Ron, that (the circled part) would be the lines marked charge fet and discharge fet. The time scale will vary depending on the frequency chosen.

Unless time scale means some thing else?

But I now think there may be a flaw in this. Have to relook at it due to something Praondevou pointed out.
 
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