Invert a PWM signal

Discussion in 'General Electronics Chat' started by SVS, Nov 5, 2013.

  1. SVS

    Thread Starter Member

    Aug 16, 2012
    89
    4
    Hi everyone,

    Could someone please suggest me a simple way to invert a PWM signal.

    I have a 0-5 V PWM signal with 50 % duty cycle generated from a 1- channel pulse train output terminal.

    I would like to invert this signal in-order to feed my H-bridge circuit.
    I thought of using a NOT gate IC 7404.

    Is that the right way or is there a better solution.?

    Thank you!!
     
  2. Art

    Distinguished Member

    Sep 10, 2007
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    SVS likes this.
  3. SVS

    Thread Starter Member

    Aug 16, 2012
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  4. tracecom

    AAC Fanatic!

    Apr 16, 2010
    3,871
    1,394
    Art has provided a link to a single transistor inverter. The hex inverter you linked to is surface mount and has five more gates than you need, but yes, it would work.
     
  5. MrChips

    Moderator

    Oct 2, 2009
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    Why do you want to invert a PMW signal with 50% duty cycle?
    You will end up with 50% duty cycle.

    Edit: Sorry, I just read you want to drive an H-bridge.

    Use another port pin or use a single transistor.

    Note that you will end up with phase delays.

    Use a toggle flip-flop to avoid phase shifts. Or use an mcu that generates complementary PMW with controlled delays.
     
  6. SVS

    Thread Starter Member

    Aug 16, 2012
    89
    4
    Please see my attachment( To obtain a signal similar to that ) and drive a H bridge circuit.
    sorry , I wasn t specific.
     
  7. SVS

    Thread Starter Member

    Aug 16, 2012
    89
    4
    Thank you Mr.chips for the suggestion.
    My first choice was to use a J-K flip flop in toggle mode .
    But I couldn t understand the IC's functionality properly. So, I ended up with this Inverter IC.

    could you please provide me with some information about toggle mode operation of J-K flip flop ?
     
  8. MrChips

    Moderator

    Oct 2, 2009
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    To make a toggle flip-flop from a J-K flip-flop, connect both J and K inputs high.
    The output frequency will be half the input clock frequency.
     
  9. SVS

    Thread Starter Member

    Aug 16, 2012
    89
    4
    Thank you for the response.
    If I understood right ,
    Please check my attachment where I just took an example and tried to figure the concept you mentioned.
     
  10. MrChips

    Moderator

    Oct 2, 2009
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    That is correct.

    You should also connect pins 2 and 3 to high to prevent spurious noise from messing up the flip-flop.

    Also connect pin-6, 2CLK to ground to disable the second flip-flop.
     
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  11. crutschow

    Expert

    Mar 14, 2008
    13,052
    3,244
    The small phase-delay to the PWM digital signal from the propagation delay of an inverter is not likely to be a problem in most PWM applications since the PWM carrier frequency is normally much higher than the modulation frequency.
     
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