Interfacing DDR3 SDRAM memory controller to an Virtex 6 FPGA

Discussion in 'General Electronics Chat' started by ideas, Apr 21, 2012.

  1. ideas

    Thread Starter New Member

    Mar 16, 2012
    7
    0
    Hi,
    can any 1 say me, IS MIG core generator usage for this problem is correct?
    By using MIG can we generate a code for interfacing Controller to an FPGA?
     
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