intel memory addressing(effective address or offset) in 16 bit protected or real mode

Discussion in 'Programmer's Corner' started by logicman112, May 9, 2010.

  1. logicman112

    Thread Starter Active Member

    Dec 27, 2008
    69
    2
    Intel-desktop processors like core to quad, i7....

    My question is how we can write effective address in 16, 32 or 64 bit modes. We know that the following is a valid effective address in 16 bit IA-32 protected:
    [BX+SI]+disp8
    Can we specify: [BH+SI]+disp8 as an address?

    Also suppose we write a code for IA-32 protected, the following is a valid effective address:
    [EAX]+disp32

    But is , [AX]+disp32 a valid valid effective address? how about [AL]+disp32?

    In real mode(16-bit) we have [BX]+disp8 but is "[BL]+disp8" valid?

    And my last question is that how you write a valid address in 64 bit mode?
     
  2. retched

    AAC Fanatic!

    Dec 5, 2009
    5,201
    312
    Are you just asking generally or are you using a specific compiler and or a specific task at hand?

    For instance:
    In which compiler?
     
  3. 311499

    New Member

    Apr 29, 2010
    5
    0
    For the 80286 and 80386, [BX+SI+disp8] is valid. [BH+SI+disp8] is not.
    As far as I know, no x86 processors support 8 bit registers as part of
    the effective address.

    Again, the address [AL+disp32] contains an 8 bit register and is not valid
    on the 80386. [EAX+disp32] on the other hand, is supported by the 80386.
    [AX+disp32] is not valid on the 80386.

    I'm not familiar with the 64 bit mode of newer processors.
    [BL+disp8] contains an 8 bit register and is not a valid effective address on
    the 80286 or 80386.
     
  4. logicman112

    Thread Starter Active Member

    Dec 27, 2008
    69
    2
    it seems that effective address is considered by some specific registers in different code segments. Like in 32 bits, [EAX] is valid and instruction format is decoded by using EAX and no format exists for AX.

    in 64 , default is 32 and we can use EAX, EBX,... but with REX.w=1, we can use [RAX], i mean CPU considers RAX when decoding the instruction.

    If i am wrong please let me know. Thank you.
     
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