INTCON - mapping the PIC18F45K50.h with the PIC18C reference manual and getting a few oddities

Discussion in 'Embedded Systems and Microcontrollers' started by Hoylegj, Mar 24, 2016.

  1. Hoylegj

    Thread Starter New Member

    Mar 10, 2016
    16
    1
    Working with a PIC18F45K50, I can not find a reference manual named the same, only a PIC18C manual.

    I've Tried to map the PIC18F45K50.h with the PIC18C reference manual and getting a few oddities

    The bit names do not match, but are they the same, i.e. bit wise functionally the same if you map to the new bit name?

    Many Thanks Geoff.

    Code (C):
    1. /* =====45K50.h  ===  PIC18C Doc
    2. INTCON
    3. 1)  IOCIF:1;  // bit 0 RBIF:
    4. 2)  IOCIE:1;  // bit 3 RBIE:
    5.  
    6.  
    7. INTCON2
    8. 3)  IOCIP:1;  // bit 0 RBIP:
    9. 4)  NOT_RBPU:1; // bit 7 RBPU:
    10. */
    11.  
    12.  
    13. extern volatile near unsigned char  INTCON;
    14. extern volatile near union {
    15.   struct {
    16.   unsigned IOCIF:1;  // bit 0 RBIF: RB Port Change Interrupt Flag bit
    17.   //  1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
    18.   //  0 = None of the RB7:RB4 pins have changed state
    19.   unsigned INT0IF:1;  // bit 1 INT0IF: INT0 External Interrupt Flag bit
    20.   //  1 = The INT0 external interrupt occurred (must be cleared in software)
    21.   //  0 = The INT0 external interrupt did not occur
    22.   unsigned TMR0IF:1;  // bit 2  TMR0 Overflow Interrupt Flag bit
    23.   //  1 = TMR0 register has overflowed (must be cleared in software)
    24.   //  0 = TMR0 register did not overflow
    25.   unsigned IOCIE:1;  // bit 3 RBIE: RB Port Change Interrupt Enable bit
    26.   //  1 = Enables the RB port change interrupt
    27.   //  0 = Disables the RB port change interrupt
    28.   unsigned INT0IE:1;  // bit 4 INT0IE: INT0 External Interrupt Enable bit
    29.   //  1 = Enables the INT0 external interrupt
    30.   //  0 = Disables the INT0 external interrupt
    31.   unsigned TMR0IE:1;  // bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit
    32.   //  1 = Enables the TMR0 overflow interrupt
    33.   //  0 = Disables the TMR0 overflow interrupt
    34.   unsigned PEIE_GIEL:1;// bit 6 PEIE/GEIL: Peripheral Interrupt Enable bit
    35.   //  When IPEN = 0:
    36.   //  1 = Enables all un-masked peripheral interrupts
    37.   //  0 = Disables all peripheral interrupts
    38.   unsigned GIE_GIEH:1; // bit 7 GIE/GIEH: Global Interrupt Enable bit
    39.   //  When IPEN = 0:
    40.   //  1 = Enables all un-masked interrupts
    41.   //  0 = Disables all interrupts
    42.   //  When IPEN = 1:
    43.   //  1 = Enables all interrupts
    44.   //  0 = Disables all interrupts
    45.   };
    46.   struct {
    47.   unsigned :1;
    48.   unsigned INT0F:1;
    49.   unsigned T0IF:1;
    50.   unsigned :1;
    51.   unsigned INT0E:1;
    52.   unsigned T0IE:1;
    53.   unsigned PEIE:1;
    54.   unsigned GIE:1;
    55.   };
    56.   struct {
    57.   unsigned :6;
    58.   unsigned GIEL:1;
    59.   unsigned GIEH:1;
    60.   };
    61. } INTCONbits;
    62.  
    63.  
    64. extern volatile near unsigned char  INTCON2;
    65. extern volatile near union {
    66.   struct {
    67.   unsigned IOCIP:1;  // bit 0 RBIP: RB Port Change Interrupt Priority bit
    68.   //  1 = RB Port Change Interrupt is a high priority event
    69.   //  0 = RB Port Change Interrupt is a low priority event
    70.   unsigned :1;
    71.   unsigned TMR0IP:1;  // bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit
    72.   //  1 = TMR0 Overflow Interrupt is a high priority event
    73.   //  0 = TMR0 Overflow Interrupt is a low priority event
    74.   unsigned :1;
    75.   unsigned INTEDG2:1;  // bit 4 INTEDG2: External Interrupt2 Edge Select bit
    76.   //  1 = Interrupt on rising edge
    77.   //  0 = Interrupt on falling edge
    78.   unsigned INTEDG1:1;  // bit 5 INTEDG1: External Interrupt1 Edge Select bit
    79.   //  1 = Interrupt on rising edge
    80.   //  0 = Interrupt on falling edge
    81.   unsigned INTEDG0:1;  // bit 6 INTEDG0:External Interrupt0 Edge Select bit
    82.   //  1 = Interrupt on rising edge
    83.   //  0 = Interrupt on falling edge
    84.   unsigned NOT_RBPU:1; // bit 7 RBPU: PORTB Pull-up Enable bit
    85.   //  1 = All PORTB pull-ups are disabled
    86.   //  0 = PORTB pull-ups are enabled by individual port latch values
    87.   };
    88.   struct {
    89.   unsigned :2;
    90.   unsigned T0IP:1;
    91.   unsigned :4;
    92.   unsigned RBPU:1;
    93.   };
    94. } INTCON2bits;
    95.  
    96.  
    97. extern volatile near unsigned char  INTCON3;
    98. extern volatile near union {
    99.   struct {
    100.   unsigned INT1IF:1;  // bit 0 INT1IF: INT1 External Interrupt Flag bit
    101.   //  1 = The INT1 external interrupt occurred (must be cleared in software)
    102.   //  0 = The INT1 external interrupt did not occur
    103.   unsigned INT2IF:1;  // bit 1 INT2IF: INT2 External Interrupt Flag bit
    104.   //  1 = The INT2 external interrupt occurred (must be cleared in software)
    105.   //  0 = The INT2 external interrupt did not occur
    106.   unsigned :1;
    107.   unsigned INT1IE:1;  // bit 3 INT1IE: INT1 External Interrupt Enable bit
    108.   //  1 = Enables  the INT1 external interrupt
    109.   //  0 = Disables the INT1 external interrupt
    110.   unsigned INT2IE:1;  // bit 4 INT2IE: INT2 External Interrupt Enable bit
    111.   //  1 = Enables  the INT1 external interrupt
    112.   //  0 = Disables the INT1 external interrupt
    113.   unsigned :1;
    114.   unsigned INT1IP:1;  // bit 6 INT1IP: INT1 External Interrupt Priority bit
    115.   //  1 = INT1 External Interrupt is a high priority event
    116.   //  0 = INT1 External Interrupt is a low priority event
    117.   unsigned INT2IP:1;  // bit 7 INT2IP: INT2 External Interrupt Priority bit
    118.   //  1 = INT2 External Interrupt is a high priority event
    119.   //  0 = INT2 External Interrupt is a low priority event
    120.   };
    121.   struct {
    122.   unsigned INT1F:1;
    123.   unsigned INT2F:1;
    124.   unsigned :1;
    125.   unsigned INT1E:1;
    126.   unsigned INT2E:1;
    127.   unsigned :1;
    128.   unsigned INT1P:1;
    129.   unsigned INT2P:1;
    130.   };
    131. } INTCON3bits;
    Moderators note: used code tags for C
     
    Last edited by a moderator: Mar 24, 2016
  2. JohnInTX

    Moderator

    Jun 26, 2012
    2,338
    1,018
    The 18C reference manual is very dated and should be used only for general information. The datasheet for the exact chip you are using should be the the reference you use. Register and bit names can change as features get updated, added etc. The names in the datasheet will match those in the .h file for your chip. Also, later compilers like XC8 can define the PIC registers differently than earlier compilers did so the constructs shown in the old reference manual may be problematic in current stuff.

    Caveat: on very rare occasions, the .h file will have a discrepancy in the naming vs. the datasheet. Usually, problems will be your own but it is sometimes worthwhile to review the .h to see if naming conventions have changed. Sometimes the .h files get changed before the datasheet catches up. It does not happen very often.

    Good luck.
     
  3. MaxHeadRoom

    Expert

    Jul 18, 2013
    10,494
    2,364
    The bit names are all in the P18F45K50.INC file if this is any help.
    Max.
     
  4. Hoylegj

    Thread Starter New Member

    Mar 10, 2016
    16
    1
    Thanks Gents
     
  5. dannyf

    Well-Known Member

    Sep 13, 2015
    1,766
    355
    Try microchip website. The data sheet is there
     
  6. JohnInTX

    Moderator

    Jun 26, 2012
    2,338
    1,018
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