input edge rise and fall time and propagation delay

Discussion in 'Embedded Systems and Microcontrollers' started by nileshkhupase, Jun 15, 2011.

  1. nileshkhupase

    Thread Starter Member

    Mar 22, 2011

    i want to ask that how input edge rise and fall time and propagation delay can affect my design.
    suppose i have a microcontroller working at 16Mhz and i am using a octal latch with input edge rise time and fall time of 125 mV/ns and having propagation delay of 11nS for latching 8-bit address on a multiplexed what should be the minimum time period for ALE signal from microcontroller so that latch outputs can make proper transitions.does it will work fine if i take octal latch with 40mV/ns ?
  2. ErnieM

    AAC Fanatic!

    Apr 24, 2011
    If you have any specific devices in mind you should list them, and links to the data sheets are a good thing too.

    What latch is this? Is 16MHz the instruction rate?

    Generally the two parameters of the latch you need to meet are data set-up time and data hold time. Set up is the time before the latching signal (ALE?) is enabled where the data must be valid and stable, and hold time is the time after the latch signal where the data remains valid.

    Looking at the first device a search of "octal latch" found gave me a 74F573/74F574 device. This has a set up of 2nS minimum and a hold time of 4nS minimum. Here "minimum" means just that: you are free to make it longer, as long as you wish.

    If 16MHz is the instruction rate then the fastest the pins can change is the inverse, 62.5nS. So as long as you do not bang the ALE in the same instruction as the data everything is fine, as your setup and hold times are the same as the instruction rate.

    I don't see what you are getting at with the rise and fall times. While some latches have a minimum rise or fall time spec but if you are driving with 40mV/nS (40 megavolts/second!) you are good.