I dont understand what you mean by that.

 

I dont understand what you mean by that.

ok look this code

module acc(D,ld3,clk,Q);
input D;
input ld3;
input clk;
output  Q;
reg[3:0] Q;
always @(posedge clk)
        begin
           if (ld3==1) Q <= D;
        end
endmodule
module tempacc(D,ld4,clk,Q);
input D;
input ld4;
input clk;
output  Q;
reg[3:0] Q;
always @(posedge clk)
        begin
           if (ld4==1) Q <= D;
        end
endmodule
module tempaccreg(D,ld5,clk,Q);
input D;
input ld5;
input clk;
output  Q;
reg[3:0] Q;
always @(posedge clk)
        begin
           if (ld5==1) Q <= D;
        end
endmodule

here I am using same input (D, clk ) and output Q in every modules . ANd I have used always block in every modules I think its useless

 

Each D and clk exists only inside that module. In other words, the D in tempacc is completely not related to D in tempaccreg. Two completely different signals, even though they have the same name.
A module is similar to a function in C or pascal, if you want to look at it this way. Or similar to a component like for example 74HC04 ttl chip.

When you write this:

module register(D,ld,clk,Q);
input D;
input ld;
input clk;
output  Q;
reg[3:0] Q;
always @(posedge clk)
  begin
  if (ld==1) Q <= D;
  end
endmodule

You define a component that has three inputs and one output.

Then when you write

register R1(A,ld1,clk,B);
register R2(B,ld2,clk,C);

inside the core_v you use the component "register" two times. One will be called R1 and the other R2. Wire B connects the output of R1 to the input of R2

 

Each D and clk exists only inside that module. In other words, the D in tempacc is completely not related to D in tempaccreg. Two completely different signals, even though they have the same name.
A module is similar to a function in C or pascal, if you want to look at it this way. Or similar to a component like for example 74HC04 ttl chip.

When you write this:

module register(D,ld,clk,Q);
input D;
input ld;
input clk;
output  Q;
reg[3:0] Q;
always @(posedge clk)
  begin
  if (ld==1) Q <= D;
  end
endmodule

You define a component that has three inputs and one output.

Then when you write

register R1(A,ld1,clk,B);
register R2(B,ld2,clk,C);

inside the core_v you use the component "register" two times. One will be called R1 and the other R2. Wire B connects the output of R1 to the input of R2[/QUOTE

ok I think I understood how does one component connect with another
Do you want to give me another assignment ?