input and output signal for microcontroller

Discussion in 'General Electronics Chat' started by vead, Sep 15, 2014.

  1. vead

    Thread Starter Active Member

    Nov 24, 2011
    621
    8
    I want to write input and output for microcontroller in verilog langugae

    I have done some work

    Microcontroller has following function

    · ALU

    · Decoder

    · Port

    · Counter

    · Interrupt

    · Accumulator

    · Stack pointer

    · Data pointer

    · Special function register

    · Serial communication

    · Internal rom

    · External rom

    · Internal ram

    · External Ram


    Verilog code
    Code (Text):
    1.  
    2. Module mcu (clk, rst, en, p_in, p_out, t_in, t_out, i_in,i_out, rx_in, tx_out, a,b, s0,s1,s2, a0,a1,a2,d0,d1,d2,d3,d4,d5,d6.....etc )
    3.  
    4. Rst= reset input
    5. Clk=  clock input
    6. En= enable input
    7.  
    8. Port
    9. P_in=port input
    10. P_out= port output
    11.  
    12. Timer
    13. T_in = timer input
    14. T_out = timer output
    15.  
    16. Interrupt
    17. i_in= input for interrupt
    18. i_out,= output for interrupt
    19.  
    20. ALU
    21. A=input
    22. B=input
    23. So=input
    24. S1=input
    25. S2=input
    26. F=output
    27.  
    28. Decoder
    29. opcode_in
    30. opcode_out
    31.  
    32. ram
    33. wr
    34. wd
    35.  
    36. ram
    37. read
    38. write
    39. enable
    40.  
    Can anyone tell me how to write input and output for microcontroller in verilog langugae ?
     
    Last edited: Sep 16, 2014
  2. tshuck

    Well-Known Member

    Oct 18, 2012
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    675
    Any Verilog tutorial will show you how to define inputs and outputs...
     
  3. vead

    Thread Starter Active Member

    Nov 24, 2011
    621
    8
    thanks for quick response I know how does we write input and output for gates , flip flop adder, decoder counter, alu ,....etc but I don't understand for microcontroller
     
  4. tshuck

    Well-Known Member

    Oct 18, 2012
    3,531
    675
    If you are still attempting a soft processor (e.g. a microcontroller implemented on a FPGA, or some other PLD), then the microcontroller is comprised of many smaller modules (e.g. I/O direction control register, ALU, etc.).

    The soft microcontroller is arranged in much the same way as many other Verilog components are: they have prescribed inputs and outputs as part of the architecture - you just need to route signals where they need to then go.

    Make a top level, Verilog module called microcontroller.v and put everything the controller requires inside (instantiate each instance) and connect the various components together as they should be.
     
    vead likes this.
  5. tshuck

    Well-Known Member

    Oct 18, 2012
    3,531
    675
    This is were a tutorial comes in handy.

    See here.

    You first instantiate a module, then start adding the requisite components. Someone that learned Verilog should be able to do this (specific syntax notwithstanding, but the general idea should be there).
    Code (Text):
    1.  
    2. module microcontroller (
    3. clk,
    4. rst_0,
    5. PA1,
    6. //etc...
    7. );
    8.  
    9. //Input declaration
    10. input clk;
    11. input rst_0;
    12. //etc.
    13.  
    14. //Output declaration
    15. //define outputs
    16.  
    17. //Interconnect signals
    18. wire GlobalOE_0;
    19. wire PA[7:0];
    20. wire PB[7:0];
    21. wire PA_control;
    22. wire PB_control
    23.  
    24. //I/O controller
    25. IOController ioCntrl(
    26. PA_control,
    27. PB_control,
    28. //etc.
    29. );
    30.  
    31. //Add I/O Port A
    32. IOPort PA(
    33. PA[7:0],
    34. PA_control,
    35. GlobalOE_0
    36. );
    37.  
    38. //Add I/O Port B
    39. IOPort PB(
    40. PB[7:0],
    41. PB_control,
    42. GlobalOE_0
    43. );
    44.  
    45. //etc.
    46.  
    47. End module;
    48.  
    Keep in mind I typically use VHDL, so the syntax may be off...
     
    vead likes this.
  6. vead

    Thread Starter Active Member

    Nov 24, 2011
    621
    8
    it helped me a lot thank for giving general idea
    Code (Text):
    1. Module mcu (clk, rst, en, p_in, p_out, t_in, t_out, i_in,i_out, rx_in, tx_out ,a0,a1,a2,d0,d1,d2,d3,d4,d5,d6,d7,a,b,s0,s1,s2,f,........etc);
    2. Rst= reset input
    3. Clk=  clock input
    4. En= enable input
    5. Port
    6. P_in=port input
    7. P_out= port output
    8.  
    9. Timer
    10. T_in = timer input
    11. T_out = timer output
    12.  
    13. Interrupt
    14. i_in= input for interrupt
    15. i_out,= output for interrupt
    16.  
    17. ram
    18. wr
    19. wd
    20.  
    21. ram
    22. read
    23. write
    24. enable
    25.  
    26. Module alu (a,b,s0,s1,s2 f);
    27. Input a,b,s0,s1,s2;
    28. Output f;
    29. Reg [3:0];
    30. Always @(s0,s1,s2);
    31. Begian
    32. Case (s0,s1,s2);
    33. 3b’000 :f=(a&b);
    34. 3b’001:f= (a|b);
    35. 3b’010 :f= ~(a&b);
    36. 3b’011 :f= ~ (a|b);
    37. 3b’100:f=(a^b);
    38. 3b’101: f=(a*b);
    39. 3b’110: f=(a+b);
    40. 3b’111:f=(a-b );
    41. End case
    42. End module
    43.  
    44.  
    45.  
    46. Module decoder (a2,a1,a0, d7,d6,d5,d4,d3,d2,d1,d0);
    47. Input a2,a1,a0;
    48. Output d7,d6,d5,d4,d3,d2,d1,d0;
    49. Wire [7:0];
    50. Always @(a2,a1,a0);
    51. Begin
    52. Case (a2,a1,a0);
    53. 4’b000:( d7,d6,d5,d4,d3,d2,d1,d0)=00000001;
    54. 4’001: (d7,d6,d5,d4,d3,d2,d1,d0)=00000010;
    55. 4’b010: (d7,d6,d5,d4,d3,d2,d1,d0)=00000100;
    56. 4’b011: (d7,d6,d5,d4,d3,d2,d1,d0)=00001000;
    57. 4’b100:( d7,d6,d5,d4,d3,d2,d1,d0)=00010000;
    58. 4’b101:( d7,d6,d5,d4,d3,d2,d1,d0)=00100000;
    59. 4’b110: (d7,d6,d5,d4,d3,d2,d1,d0)=01000000;
    60. 4’b111: (d7,d6,d5,d4,d3,d2,d1,d0)=10000000;
    61. Endcase
    62. Endmodule
    63.  
    64.  
    first I have define input output example ALU, DECODER, PORT ....etc
    then I made code for inner part example ALU, decoder
    how to route alu with decoder . (I am asking for handy code
     
  7. tshuck

    Well-Known Member

    Oct 18, 2012
    3,531
    675
    How did you design your decoder to interact with the ALU? Follow whatever logic diagram you made when designing the controller.

    I'm confused as to why your are asking us about your design. You are the one making this controller.

    If you made the pieces without being sure of how to connect them, you need to spend some of your time figuring it out. Simply defining things and attempting to cobble them together later is a good way to waste a lot of time. Design with a plan.
     
  8. vead

    Thread Starter Active Member

    Nov 24, 2011
    621
    8
    decoder connect with address bus , data bus ,control bus
    I have spend lot of time. I am not designing for company.
    i am student I don't care what I will make. I just want to learn way ,
    I know designing controller is not easy . It need more reading and practice
    I did search more but I could not find how to add alu , decoder , program counter and other
    so I just wrote code for alu, and decoder
    so I did ask here how to connect ALU with decoder
     
    Last edited: Sep 16, 2014
  9. tshuck

    Well-Known Member

    Oct 18, 2012
    3,531
    675
    In a few minutes of searching, I've found a great deal of information showing what to do.

    See the following:

    I'd recommend you stop getting ahead of yourself and latching on to the words you see and learn the design principles from the ground up, otherwise, you'll have only the vocabulary with none of the understanding.
     
    absf and vead like this.
  10. vead

    Thread Starter Active Member

    Nov 24, 2011
    621
    8
    ok thanks for your every quick response and valuable time
    now i think, I have to start write code . I will write code and I will compile code
     
  11. vead

    Thread Starter Active Member

    Nov 24, 2011
    621
    8
    sorry but still I am confused I don't see any statement that show that my controller is connected with ALU, decoder
    Code (Text):
    1.  
    2.  
    3. Module mcu (clk, rst, en, p_in, p_out, t_in, t_out, i_in,i_out, rx_in, tx_out ,a0,a1,a2,d0,d1,d2,d3,d4,d5,d6,d7,a,b,s0,s1,s2,f,........etc);
    4. Rst= reset input
    5. Clk=  clock input
    6. En= enable input
    7. Port
    8. P_in=port input
    9. P_out= port output
    10.  
    11. Timer
    12. T_in = timer input
    13. T_out = timer output
    14.  
    15. Interrupt
    16. i_in= input for interrupt
    17. i_out,= output for interrupt
    18.  
    19. ram
    20. wr
    21. wd
    22.  
    23. ram
    24. read
    25. write
    26. enable
    27.  
    28. Module alu (a,b,s0,s1,s2 f);
    29. Input a,b,s0,s1,s2;
    30. Output f;
    31. Reg [3:0];
    32. Always @(s0,s1,s2);
    33. Begian
    34. Case (s0,s1,s2);
    35. 3b’000 :f=(a&b);
    36. 3b’001:f= (a|b);
    37. 3b’010 :f= ~(a&b);
    38. 3b’011 :f= ~ (a|b);
    39. 3b’100:f=(a^b);
    40. 3b’101: f=(a*b);
    41. 3b’110: f=(a+b);
    42. 3b’111:f=(a-b );
    43. End case
    44. End module
    45.  
    46.  
    47.  
    48. Module decoder (a2,a1,a0, d7,d6,d5,d4,d3,d2,d1,d0);
    49. Input a2,a1,a0;
    50. Output d7,d6,d5,d4,d3,d2,d1,d0;
    51. Wire [7:0];
    52. Always @(a2,a1,a0);
    53. Begin
    54. Case (a2,a1,a0);
    55. 4’b000:( d7,d6,d5,d4,d3,d2,d1,d0)=00000001;
    56. 4’001: (d7,d6,d5,d4,d3,d2,d1,d0)=00000010;
    57. 4’b010: (d7,d6,d5,d4,d3,d2,d1,d0)=00000100;
    58. 4’b011: (d7,d6,d5,d4,d3,d2,d1,d0)=00001000;
    59. 4’b100:( d7,d6,d5,d4,d3,d2,d1,d0)=00010000;
    60. 4’b101:( d7,d6,d5,d4,d3,d2,d1,d0)=00100000;
    61. 4’b110: (d7,d6,d5,d4,d3,d2,d1,d0)=01000000;
    62. 4’b111: (d7,d6,d5,d4,d3,d2,d1,d0)=10000000;
    63. Endcase
    64. Endmodule
    65.  
    66.  
    how to show in code that microcontroller is connected with some component(ALU, decoder, program counter ..) and they are wired together
     
  12. tshuck

    Well-Known Member

    Oct 18, 2012
    3,531
    675
    Why does it need to be connected? What makes you think it should be connected? What purpose would it serve?
     
    absf likes this.
  13. tshuck

    Well-Known Member

    Oct 18, 2012
    3,531
    675
    See my previous post...
    Note the portion labeled "Interconnect Signals" - this is where the signal called "PA_control" (declared as a wire) is instantiated. By following all of the places this signal name is used, we know that IOPort PA is connected to the IOController.

    You connect modules at the same hierarchical levels with wires. Modules lower in the hierarchy are connected by modifying/connecting to inputs & outputs from the parent module.
     
    Last edited: Sep 17, 2014
  14. vead

    Thread Starter Active Member

    Nov 24, 2011
    621
    8
    ok I am trying ,look at below
    Code (Text):
    1.  
    2. Module mcu (clk, rst, en, p_in, p_out, t_in, t_out, i_in,i_out, rx_in, tx_out ,a0,a1,a2,d0,d1,d2,d3,d4,d5,d6,d7,a,b,s0,s1,s2,f,........etc);
    3. //Input, output  declaration
    4. Rst= reset input
    5. Clk=  clock input
    6. En= enable input
    7. Port
    8. P_in=port input
    9. P_out= port output
    10.  
    11. Timer
    12. T_in = timer input
    13. T_out = timer output
    14.  
    15. Interrupt
    16. i_in= input for interrupt
    17. i_out,= output for interrupt
    18.  
    19. ram
    20. wr
    21. wd
    22.  
    23. ram
    24. read
    25. write
    26. enable
    27.  
    28. //Interconnect signals
    29. wire alu [3:0]
    30. wire decoder [7:0]
    31.  
    32. // add alu
    33. Mcu_alu (a,b,s0,s1,s2 f);
    34. Input a,b,s0,s1,s2;
    35. Output f;
    36. Reg [3:0];
    37. Always @(s0,s1,s2);
    38. Begian
    39. Case (s0,s1,s2);
    40. 3b’000 :f=(a&b);
    41. 3b’001:f= (a|b);
    42. 3b’010 :f= ~(a&b);
    43. 3b’011 :f= ~ (a|b);
    44. 3b’100:f=(a^b);
    45. 3b’101: f=(a*b);
    46. 3b’110: f=(a+b);
    47. 3b’111:f=(a-b );
    48. End case;
    49.  
    50.  
    51. //Add decoder
    52.  
    53. Mcu_decoder (a2,a1,a0, d7,d6,d5,d4,d3,d2,d1,d0);
    54. Input a2,a1,a0;
    55. Output d7,d6,d5,d4,d3,d2,d1,d0;
    56. Wire [7:0];
    57. Always @(a2,a1,a0);
    58. Begin
    59. Case (a2,a1,a0);
    60. 4’b000:( d7,d6,d5,d4,d3,d2,d1,d0)=00000001;
    61. 4’001: (d7,d6,d5,d4,d3,d2,d1,d0)=00000010;
    62. 4’b010: (d7,d6,d5,d4,d3,d2,d1,d0)=00000100;
    63. 4’b011: (d7,d6,d5,d4,d3,d2,d1,d0)=00001000;
    64. 4’b100:( d7,d6,d5,d4,d3,d2,d1,d0)=00010000;
    65. 4’b101:( d7,d6,d5,d4,d3,d2,d1,d0)=00100000;
    66. 4’b110: (d7,d6,d5,d4,d3,d2,d1,d0)=01000000;
    67. 4’b111: (d7,d6,d5,d4,d3,d2,d1,d0)=10000000;
    68. Endcase
    69. Endmodule
     
  15. kubeek

    AAC Fanatic!

    Sep 20, 2005
    4,669
    804
    You should use a much shorter and simpler example to see how it should be done.
    Code (Text):
    1. module HalfAdder (A,B,S,C)
    2.   input A,B;
    3.   output S,C;
    4.  
    5.   xor sum (S,A,C);
    6.   and Carry(C,A,B);
    7. endmodule
    Code (Text):
    1. module FullAdder(A,B,Cin,S,Cout);
    2.   input A, B, Cin;
    3.   output S, Cout;
    4.   wire S1, C1, C2;
    5.  
    6.   HalfAdder HA1(A, B, S1, C1);
    7.   HalfAdder HA2(S1, Cin, S, Cout);
    8.   or Carry (Cout, C1, C2);
    9. endmodule
    Here you can see, that in the module FullAdder you are using two instances of the component half adder, and zou can see how they are connected to the module's inputs and outputs and how they are connected together.

    You should keep each module in separate file, it makes debugging much easier.

    Now, try and make a 4-bit adder using four instances of FullAdder, and connect each Cout to the next Cin.

    I took these examples from here (part 3) http://3bdalladalleh.wordpress.com/...ith-verilog-hdl-tutorial-part-1-introduction/ which seems like a nice tutorial.
     
  16. vead

    Thread Starter Active Member

    Nov 24, 2011
    621
    8
    look this work

    Code (Text):
    1. Module mcu (clk, rst, en, p_in, p_out, t_in, t_out, i_in,i_out, rx_in, tx_out ,a0,a1,a2,d0,d1,d2,d3,d4,d5,d6,d7,a,b,s0,s1,s2,f,........etc);
    2.  
    3. //Input, output  declaration
    4. Rst= reset input
    5. Clk=  clock input
    6. En= enable input
    7. Port
    8. P_in=port input
    9. P_out= port output
    10. Timer
    11. T_in = timer input
    12. T_out = timer output
    13. Interrupt
    14. i_in= input for interrupt
    15. i_out,= output for interrupt
    16. ram
    17. wr
    18. wd
    19. ram
    20. read
    21. write
    22. enable
    23.  
    24. //Interconnect signals
    25. wire alu [3:0]
    26. wire decoder [7:0]
    27. reg counter [3:0]
    28.  
    29. // add alu
    30. Mcu_alu (a,b,s0,s1,s2 f);
    31. Input a,b,s0,s1,s2;
    32. Output f;
    33. Reg [3:0];
    34. Always @(s0,s1,s2);
    35. Begian
    36. Case (s0,s1,s2);
    37. 3b’000 :f=(a&b);
    38. 3b’001:f= (a|b);
    39. 3b’010 :f= ~(a&b);
    40. 3b’011 :f= ~ (a|b);
    41. 3b’100:f=(a^b);
    42. 3b’101: f=(a*b);
    43. 3b’110: f=(a+b);
    44. 3b’111:f=(a-b );
    45. End case;
    46.  
    47. //Add decoder
    48. Mcu_decoder (a2,a1,a0, d7,d6,d5,d4,d3,d2,d1,d0);
    49. Input a2,a1,a0;
    50. Output d7,d6,d5,d4,d3,d2,d1,d0;
    51. Wire [7:0];
    52. Always @(a2,a1,a0);
    53. Begin
    54. Case (a2,a1,a0);
    55. 4’b000:( d7,d6,d5,d4,d3,d2,d1,d0)=00000001;
    56. 4’001: (d7,d6,d5,d4,d3,d2,d1,d0)=00000010;
    57. 4’b010: (d7,d6,d5,d4,d3,d2,d1,d0)=00000100;
    58. 4’b011: (d7,d6,d5,d4,d3,d2,d1,d0)=00001000;
    59. 4’b100:( d7,d6,d5,d4,d3,d2,d1,d0)=00010000;
    60. 4’b101:( d7,d6,d5,d4,d3,d2,d1,d0)=00100000;
    61. 4’b110: (d7,d6,d5,d4,d3,d2,d1,d0)=01000000;
    62. 4’b111: (d7,d6,d5,d4,d3,d2,d1,d0)=10000000;
    63. Endcase
    64.  
    65. //add counter
    66. module up_counter(current state, next state ,clk)
    67. input current state ;
    68. input clk;
    69. output next state;
    70. reg 3:0
    71. always @ (posedge clk);
    72. begin
    73. next state <= current state +1 ;
    74. end
    75. endmodule
     
  17. kubeek

    AAC Fanatic!

    Sep 20, 2005
    4,669
    804
    nope that doesnt work. Keep the modules separate, make the definition of ALU in one file, and than use it in the MCU. Look at my example.
     
  18. vead

    Thread Starter Active Member

    Nov 24, 2011
    621
    8
    ok I try to do

    I made module separate for alu, decoder counter
    I wrote separate code for alu, decoder and counter

    Code (Text):
    1. Module mcu (clk, rst, en, p_in, p_out, t_in, t_out, i_in,i_out, rx_in, tx_out ,a0,a1,a2,d0,d1,d2,d3,d4,d5,d6,d7,a,b,s0,s1,s2,f,........etc);
    2.  
    3. //Input, output  declaration
    4. Rst= reset input
    5. Clk=  clock input
    6. En= enable input
    7. Port
    8. P_in=port input
    9. P_out= port output
    10. Timer
    11. T_in = timer input
    12. T_out = timer output
    13. Interrupt
    14. i_in= input for interrupt
    15. i_out,= output for interrupt
    16. ram
    17. wr
    18. wd
    19. ram
    20. read
    21. write
    22. enable
    23.  
    24. //Interconnect signals
    25. wire alu [3:0]
    26. wire decoder [7:0]
    27. reg counter [3:0]
    28.  
    29. // add alu
    30. module alu (a,b,s0,s1,s2 f);
    31. Input a,b,s0,s1,s2;
    32. Output f;
    33. Reg [3:0];
    34. Always @(s0,s1,s2);
    35. Begian
    36. Case (s0,s1,s2);
    37. 3b’000 :f=(a&b);
    38. 3b’001:f= (a|b);
    39. 3b’010 :f= ~(a&b);
    40. 3b’011 :f= ~ (a|b);
    41. 3b’100:f=(a^b);
    42. 3b’101: f=(a*b);
    43. 3b’110: f=(a+b);
    44. 3b’111:f=(a-b );
    45. End case;
    46.  
    47. //Add decoder
    48. Module decoder (a2,a1,a0, d7,d6,d5,d4,d3,d2,d1,d0);
    49. Input a2,a1,a0;
    50. Output d7,d6,d5,d4,d3,d2,d1,d0;
    51. Wire [7:0];
    52. Always @(a2,a1,a0);
    53. Begin
    54. Case (a2,a1,a0);
    55. 4’b000:( d7,d6,d5,d4,d3,d2,d1,d0)=00000001;
    56. 4’001: (d7,d6,d5,d4,d3,d2,d1,d0)=00000010;
    57. 4’b010: (d7,d6,d5,d4,d3,d2,d1,d0)=00000100;
    58. 4’b011: (d7,d6,d5,d4,d3,d2,d1,d0)=00001000;
    59. 4’b100:( d7,d6,d5,d4,d3,d2,d1,d0)=00010000;
    60. 4’b101:( d7,d6,d5,d4,d3,d2,d1,d0)=00100000;
    61. 4’b110: (d7,d6,d5,d4,d3,d2,d1,d0)=01000000;
    62. 4’b111: (d7,d6,d5,d4,d3,d2,d1,d0)=10000000;
    63. Endcase
    64.  
    65. //add counter
    66. module up_counter(current state, next state ,clk)
    67. input current state ;
    68. input clk;
    69. output next state;
    70. reg 3:0
    71. always @ (posedge clk);
    72. begin
    73. next state <= current state +1 ;
    74. end
    75. endmodule
     
  19. kubeek

    AAC Fanatic!

    Sep 20, 2005
    4,669
    804
    You are missing endmodule after each module. I edited your code to reflect that. See how ALU1 and CTR1 are connected together.
    edit: code tag doesnt work very well with bold letters etc.

    Module mcu (clk, rst, en, p_in, p_out, t_in, t_out, i_in,i_out, rx_in, tx_out ,a0,a1,a2,d0,d1,d2,d3,d4,d5,d6,d7,a,b,s0,s1,s2,f,........etc);

    //Input, output declaration
    Rst= reset input
    Clk= clock input
    En= enable input
    Port
    P_in=port input
    P_out= port output
    Timer
    T_in = timer input
    T_out = timer output
    Interrupt
    i_in= input for interrupt
    i_out,= output for interrupt
    ram
    wr
    wd
    ram
    read
    write
    enable

    //Interconnect signals
    wire alu [3:0]
    wire decoder [7:0]
    reg counter [3:0]

    //here you should have the insantiation of the modules you wish to use
    //for example:
    alu ALU1 (clk, rst, wire1, wire2 ...);
    up_counter CTR1 (wire1, wire2, clk)
    endmodule;




    // add alu
    module alu (a,b,s0,s1,s2 f);
    Input a,b,s0,s1,s2;
    Output f;
    Reg [3:0];
    Always @(s0,s1,s2);
    Begian
    Case (s0,s1,s2);
    3b’000 :f=(a&b);
    3b’001:f= (a|b);
    3b’010 :f= ~(a&b);
    3b’011 :f= ~ (a|b);
    3b’100:f=(a^b);
    3b’101: f=(a*b);
    3b’110: f=(a+b);
    3b’111:f=(a-b );
    End case;
    endmodule


    //Add decoder
    Module decoder (a2,a1,a0, d7,d6,d5,d4,d3,d2,d1,d0);
    Input a2,a1,a0;
    Output d7,d6,d5,d4,d3,d2,d1,d0;
    Wire [7:0];
    Always @(a2,a1,a0);
    Begin
    Case (a2,a1,a0);
    4’b000: (d7,d6,d5,d4,d3,d2,d1,d0)=00000001;
    4’001: (d7,d6,d5,d4,d3,d2,d1,d0)=00000010;
    4’b010: (d7,d6,d5,d4,d3,d2,d1,d0)=00000100;
    4’b011: (d7,d6,d5,d4,d3,d2,d1,d0)=00001000;
    4’b100: (d7,d6,d5,d4,d3,d2,d1,d0)=00010000;
    4’b101: (d7,d6,d5,d4,d3,d2,d1,d0)=00100000;
    4’b110: (d7,d6,d5,d4,d3,d2,d1,d0)=01000000;
    4’b111: (d7,d6,d5,d4,d3,d2,d1,d0)=10000000;
    Endcase
    endmodule

    //add counter
    module up_counter(current state, next state ,clk)
    input current state ;
    input clk;
    output next state;
    reg 3:0
    always @ (posedge clk);
    begin
    next state <= current state +1 ;
    end
    endmodule
     
    Last edited by a moderator: Sep 18, 2014
    vead likes this.
  20. vead

    Thread Starter Active Member

    Nov 24, 2011
    621
    8
    look at this code there is another way to connect one component to other
    Is it correct way to connect with another ,?
    Code (Text):
    1. module mcu_8051 (rst, clk ,
    2.  
    3. // interrupt interface
    4.                 int0_i,
    5.                 int1_i,
    6. // port interface
    7.   `ifdef mcu_port
    8.         `ifdef mcu_port0
    9.                 p0_i,
    10.                 p0_o,
    11.         `endif
    12.         `ifdef mcu_port1
    13.                 p1_i,
    14.                 p1_o,
    15.         `endif
    16.         `ifdef mcu_port2
    17.                 p2_i,
    18.                 p2_o,
    19.         `endif
    20.         `ifdef mcu_port3
    21.                 p3_i,
    22.                 p3_o,
    23.         `endif
    24.   `endif
    25. // serial interface
    26.         `ifdef mcu_uart
    27.                 rxd_i, txd_o,
    28.         `endif
    29. // counter interface
    30.         `ifdef mcu_tc01
    31.                 t0_i, t1_i,
    32.         `endif
    33.         `ifdef OC8051_tc2
    34.                 t2_i, t2ex_i,
    35.         `endif
    36.  
    what is mean by ifdef and endif ?
     
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