Hi all.
This has nothing to do with PCs, but for units with a processor, ram, firmware rom, watchdog, fplga, reset circuit and peripheric DSPs; where the rom is typically loaded to ram and executed at power-on.
What techniques are convenient to follow, after confirming presence of power supply, clock, reset, data and address lines activity ? What if there is no activity on data lines; or keeps resetting; or halts, ...?
Buses carrying signals to multiple chips make uncertain the verification and discerning the failure. Any methodical suggestions please ?
Miguel
This has nothing to do with PCs, but for units with a processor, ram, firmware rom, watchdog, fplga, reset circuit and peripheric DSPs; where the rom is typically loaded to ram and executed at power-on.
What techniques are convenient to follow, after confirming presence of power supply, clock, reset, data and address lines activity ? What if there is no activity on data lines; or keeps resetting; or halts, ...?
Buses carrying signals to multiple chips make uncertain the verification and discerning the failure. Any methodical suggestions please ?
Miguel