Initial state of 4043 latch outputs

Discussion in 'General Electronics Chat' started by Dave65, Nov 2, 2015.

  1. Dave65

    Thread Starter New Member

    Nov 1, 2015
    4
    0
    Hi,

    I'm powering up a 4043 SR latch with S and R both tied low. The output is always high at power up which feels a bit counter intuitive, given that S has not been given a high.

    I understand that the S and R lows would cause the output to latch in whatever state the output was, but why is this high (at power up?)

    I suppose my question is, is this expected SR latch (4043 in particular) behaviour? If it is then I'll need to implement something to give R a brief high at power up to force the output low.

    Many thanks
     
  2. RamaD

    Active Member

    Dec 4, 2009
    254
    33
    There is nothing mentioned in the data sheet about the output state with both R & S inputs low while powering on. The behaviour could be different for parts from different manufacturers. If any known output state is required on power on, then that must be forced like you had suggested.
     
  3. Alec_t

    AAC Fanatic!

    Sep 17, 2013
    5,813
    1,105
    If the latch is consistently in one particular state at power-up, and that state is the opposite of what you want, then just swap the Q and not-Q output connections.
     
    absf likes this.
  4. dl324

    Distinguished Member

    Mar 30, 2015
    3,250
    626
    A slight problem is that CD4043 don't have complementary outputs:eek:
     
  5. dl324

    Distinguished Member

    Mar 30, 2015
    3,250
    626
    If you trace the logic, you'll find that you're seeing the expected state. Below is an annotated schematic of the logic which shows why.
    SR-nor.jpg
    The only "difficulty" in analyzing latch output is you have to make an assumption. If you guess wrong, you have to walk through the logic again.
     
  6. dl324

    Distinguished Member

    Mar 30, 2015
    3,250
    626
    For completeness, here is the annotated schematic for the CD4044 NAND version:
    sr-nand.jpg
    That gate would have a LOW output with both inputs tied LOW.
     
  7. Roderick Young

    Member

    Feb 22, 2015
    408
    168
    If it's not practical to pulse R high digitally at power up, you could always put a 0.01 uF capacitor between Vdd and the R input, and drive the input through a 1k resistor. That sort of thing is frowned upon in commercial designs, but if this is a hobby project, it should work fine.
     
  8. Dave65

    Thread Starter New Member

    Nov 1, 2015
    4
    0
    Just wanted to say many thanks for everyone's replies to what was my first question in this forum :)

    I've found it a very useful site/forum and I'm sure I'll be asking further questions in future.

    Cheers
    Dave
     
Loading...