Inferred Latches in HDLs

Discussion in 'Embedded Systems and Microcontrollers' started by ActivePower, Nov 27, 2014.

  1. ActivePower

    Thread Starter Member

    Mar 15, 2012
    155
    23
    So, I recently decided to learn a HDL properly and was following one of Cornell's online courses (here, for those interested) and right in the first lecture the professor introduces something I don't yet understand - inferred latches.

    Around this time, the professor describes how an incomplete 'case' statement might lead to an inferred latch due to the behavior of the output wire to retain its previous state if no driver for it is present. I understand how that might lead it to synthesize a latch to 'hold' its last value; what I don't really get is why such behavior is expected in the first place.

    HDLs model real hardware and in case of the 'case' statement it should implement a multiplexer. If one of the mux inputs is left unconnected (as it would be if you leave out one of the switch cases) shouldn't it be left 'floating' (as in 'real' hardware)? The specified behavior of retaining the last value makes sense if you want to make it easier for a simulator but don't HDLs have a 'high Z' value too?

    I'm new to all this so any help in understanding this better would be appreciated.

    (And it has been some time since I've been here. It's definitely good to back!)
     
  2. Brownout

    Well-Known Member

    Jan 10, 2012
    2,375
    998
    HDL's do model real hardware, and they will do EXACTLY what you tell them to do. Consider the following:

    signal output;

    if(output_enable = '1') begin
    output <= TRUE;
    end

    So, what happens if output_enable is zero? You didn't specify and the HDL doesn't make any assumption. So, you get a latch, which will go to TRUE and remain so until power is disconnected. Now check this out:

    signal output;

    if(output_enable = '1') begin
    output <= TRUE;
    else
    output <= FALSE;
    end

    Now, you get what you expected in the first place. This will be a simple logical element.
     
  3. ActivePower

    Thread Starter Member

    Mar 15, 2012
    155
    23
    Do you say that because it's previous/initial state is taken to be TRUE? If there is no branch for a FALSE condition, what will it's state be upon reset and when output_enable is pulled to zero. It shouldn't be TRUE, because I never pulled the line up. Shouldn't it be unknown?

    If I didn't specify a state for the line to be in when the input condition is false, why should it assume a known state?

    I'm sorry for being so boneheaded but I seem to be having much trouble in understanding what is supposed to be a simple concept.
     
  4. Brownout

    Well-Known Member

    Jan 10, 2012
    2,375
    998
    Well, if you don't specify a condition at initialization or reset, it will remain 'unknown' until output_enable = '1'. After that, it remains 'latched' at TRUE until next power-up.
     
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