importing a new component into LTSpice

Discussion in 'General Electronics Chat' started by Pan Tong, Apr 26, 2015.

  1. Pan Tong

    Thread Starter Member

    Apr 26, 2015
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    Hello:
    is there anyone can help me on how to put a AD629B into LTSpice schematic?
    I have the .cir file for it from internet :
    http://www.analog.com/en/search.html?q=AD629B
    how can I generate a schematic footprint for it and use it in my circuit simulation?

    thanks and regards
    PT
     
  2. Sinus23

    Member

    Sep 7, 2013
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  3. Pan Tong

    Thread Starter Member

    Apr 26, 2015
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    Hi, Sinus23: thank you very much for quick rely! but I still can't figure out how to do it, I create a .asy file like upload_2015-4-27_15-5-35.png upload_2015-4-27_15-6-16.png but I still don't know how to link it to the .cir file given by the vendor:

    * Node assignments
    * non-inverting input
    * | inverting input
    * | | positive supply
    * | | | negative supply
    * | | | | output
    * | | | | | REF(-)
    * | | | | | | REF(+)
    * | | | | | | |
    .SUBCKT ad629 20 10 99 98 70 1 5

    ***EXTERNAL RESISTORS( INTERNAL TO DEVICE)***
    RF1 2 70 380E3
    RG1 10 2 378.7E3
    Rneg 2 1 21.11111E3
    RG2 20 9 378.7063E3
    RpoS 9 5 20E3
    ***input Stage***
    Ccmmr 2 0 25E-14
    ***negative input right side***
    Rc1 99 5a 2.54091E3
    Q1 5a 2 7 QX
    ***positive input left side***
    Rrc2 99 6a 2.54091E3
    Q2 6a 9b 7 QX
    ***BIAS CURRENT SOURCE***
    IEE 7 98 20E-6
    ***GAIN STAGE***
    GM1 1ref 76 5a 6a 3.52E-4
    ***ZERO/POLE***
    RG 76 1ref 8.52273E11
    CPZ 76 1ref 5.6E-12
    ***ZERO/POLE ENDS***
    ***rail_to_rail clamps***
    v1 99 13 1.600000
    d1 76 13 dx
    v2 12 98 2.210000
    d2 12 76 dx
    ***rail_to_rail clamps ENDS***
    ***MID POINT REFERENCE RESISTORS***
    Rref1 99 1mid 17E3
    Rref2 1mid 98 17E3
    Eref 1ref 0 1mid 0 1
    ***MID POINT REFERENCE RESISTORS ENDS***
    ***INPUT OFFSET VOLTAGE***
    Vos 9b 9 .005E-3
    *** END OF INPUT OFFSET VOLTAGE***
    ***OUTPUT STAGE***
    D17 76 84 DX
    VO1 84 70 .20300V
    VO2 70 85 .20300V
    D16 85 76 DX
    G30 70 99 99 76 20E-3
    G31 98 70 76 98 20E-3
    RO30 70 99 50
    RO31 98 70 50

    .MODEL QX NPN ( VA=10000,BF=5000)
    .MODEL DX D(IS=1E-12)
    .ENDS

    would you please explain in more detail ? thank you very much for help
     
  4. Pan Tong

    Thread Starter Member

    Apr 26, 2015
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    anyone know how to align the pin number of .asy file with the pin defined in .cir file? why in .cir file the pin define is like : 20, 10, 99, 98, 70 ,1, 5 instead of 1,2,3,4,5,6,7,8 like datasheet?
     
  5. Pan Tong

    Thread Starter Member

    Apr 26, 2015
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    here is my circuit of AD629B, but it seems didn't work well, anybody can help me take a look? thanks a lot !
     
  6. Alec_t

    AAC Fanatic!

    Sep 17, 2013
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    Try this change to your model file:-

    .SUBCKT ad629 +IN -IN +VS -VS O/P REF- REF+
     
  7. Pan Tong

    Thread Starter Member

    Apr 26, 2015
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    Hi, do you mean this:
    upload_2015-4-27_17-48-43.png
    instead of :
    upload_2015-4-27_17-50-2.png

    I changed, but the simulation result still same:
    upload_2015-4-27_17-51-13.png

    the current goes through R1 is green, the output from ad629 is red, why the amplitude of output is not around ~130mv ? (=13mAx10=130mV)
     
  8. Alec_t

    AAC Fanatic!

    Sep 17, 2013
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    The pin netlist order of your .asy file doesn't match the model order.
    Try this.
    Open the .asy file in Spice, right-click each pin in turn, and change the netlist order as follows:
    Pin_Netlist order
    1>6
    2>2
    3>1
    4>4
    5>7
    6>5
    7>3
     
  9. crutschow

    Expert

    Mar 14, 2008
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    The pin/port netlist order on the .asy symbol must match the order in the netlist.
    Thus, for example, since +Vs (positive supply) is the third pin listed from the left in the netlist assignment, then that pin netlist order in the .asy symbol must be 3 (as Alec noted for that and the other pins).
    The .asy file pays no attention to the actual node number in the netlist, it's just the order of the pin from the left in the .subckt line that's important.
    Edit: More correctly the .asy file ties the pin/port node on the symbol to the corresponding netlist node in the subcircuit file. Thus, for example, a main circuit connection to pin 2 on the symbol causes that point to be connected to pin 10 on the subcircuit netlist (for the given AD629 subcircuit file).

    Note that the pin name in the netlist is just a comment to tell you what the pin does. It has no effect otherwise so whether it's name is -In or Inverting Input has no effect on the circuit operation or the .asy file.

    Also typically (but not necessarily) the .asy pin/port assignment uses the function of the pin for its Label, not the number. Thus netlist order pin 2's Label would be -IN.
    If you then also make that pin name visible, it will show on the symbol and you don't need to add text for that, as you did.
     
    Last edited: Apr 27, 2015
  10. crutschow

    Expert

    Mar 14, 2008
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    I don't understand that change. :confused:
    The .SUBCKT line must contain node numbers (or names) used in the rest of the netlist.
     
  11. Alec_t

    AAC Fanatic!

    Sep 17, 2013
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    Nor do I :). Brainfart.
     
    Sinus23 likes this.
  12. Pan Tong

    Thread Starter Member

    Apr 26, 2015
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    Hello All:
    It works after the modification according your suggestion !!! thank you very much for all your help !!!

    upload_2015-4-28_9-22-35.png
     
  13. Pan Tong

    Thread Starter Member

    Apr 26, 2015
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    Hello
    trouble your guys again, I am looking for a LTSpice model of a N channel mosfet similar to IRFP150-- VDSS=100V, RDS(on)=0.04 ohm, ID=41A , anybody can share with me? thanks
     
  14. Alec_t

    AAC Fanatic!

    Sep 17, 2013
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    How about this?

    .model BSC440N10NS3 VDMOS(Rg=0.8 Vto=3.63 Rd=29.71m Rs=364u Rb=5.7m Kp=20.3 Lambda=0.03 Cgdmin=2p Cgdmax=0.13n A=0.2 Cgs=0.6n Cjo=0.49n M=0.3 Is=22.4p VJ=0.9 N=1.19 TT=60n mfg=Infineon Vds=100 Ron=44m Qg=8n)

    or this?

    .model RJK1051DPB VDMOS(Rg=1 Vto=2.4 Rd=10m Rs=20m Rb=2m Kp=300 mtriode=.5 Lambda=.3 Cgdmin=50p Cgdmax=850p Cgs=2n Cjo=2n Is=100p N=1.2 mfg=Renesas Vds=100 Ron=30m Qg=15n)

    or this?

    .model BUK9Y38100E VDMOS(Rg=1.75 Vto=2.02 Rd=30m Rs=100u Rb=2.3m Kp=100 Lambda=0 Cgdmin=70.1p Cgdmax=2.12n A=0.6 Cgs=1.8n Cjo=0.42n M=0.57 Is=0.5p VJ=0.51 N=1 TT=3n Fc=0.5 Bv=110 Ibv=250u Nbv=1 mfg=NXP Vds=100 Ron=38m Qg=21.6n)
     
  15. Pan Tong

    Thread Starter Member

    Apr 26, 2015
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    Hi, Alec:
    thank you very much for your help
     
  16. Pan Tong

    Thread Starter Member

    Apr 26, 2015
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    Anybody happen to know any LTSpice model for Filament?
    I used Rhenium wire of 0.008" diameter, coiled to make 5 turns held in a steel and ceramic support. The operate between ~1.5A and 4.5A where the minimum current is the lowest value where we see thermionic emission and the highest is the value that heats the coil so hot that it melts and fails.
     
  17. Alec_t

    AAC Fanatic!

    Sep 17, 2013
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    Sounds like you just need to model a resistor (albeit temperature-dependent perhaps?).
     
  18. Pan Tong

    Thread Starter Member

    Apr 26, 2015
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    0
    Hello:
    what is the meaning of below warning?
    upload_2015-5-5_17-58-56.png
    the simulation can't get result, when I press Esc, it display this warning.
    when I check the net list, n003 and n007 is:
    XU2 N007 N003 +15V -15V N004 OPA2251
    anything wrong with the OPA2251?

    .subckt OPA2251 1 2 3 4 5
    *
    c1 11 12 5.13E-12
    c2 6 7 470.0E-12
    dc 5 53 dx
    de 54 5 dx
    dlp 90 91 dx
    dln 92 90 dx
    dp 4 3 dx
    egnd 99 0 poly(2) (3,0) (4,0) 0 .5 .5
    fb 7 99 poly(5) vb vc ve vlp vln 0 100.0E16 -100E16 100E16 100E16 -100E16
    ga 6 0 11 12 39.58E-6
    gcm 0 6 10 99 39.58E-12
    iee 3 10 dc 1.808E-6
    hlim 90 0 vlim 1K
    q1 11 2 13 qx
    q2 12 1 14 qx
    r2 6 9 100.0E3
    rc1 4 11 80k
    rc2 4 12 80k
    re1 13 10 0.0001
    re2 14 10 0.0001
    ree 10 99 110.6E6
    ro1 8 5 2.5k
    ro2 7 99 2.5k
    rp 3 4 7.75e6
    ip 3 4 21.544uA
    vb 9 0 dc 0
    vc 3 53 dc 650.00E-3
    ve 54 4 dc 650.00E-3
    vlim 7 8 dc 0
    vlp 91 0 dc 4
    vln 0 92 dc 21
    .model dx D(Is=800.0E-18)
    .model qx PNP(Is=800.0E-18 Bf=225)
    *
    .ends OPA2251
    *
    *END MODEL OPA2251


    thank you very much for help!
     
  19. crutschow

    Expert

    Mar 14, 2008
    12,991
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    The (+) input on the op amp is open. That may cause the problem.
    In general, Spice does not like floating nodes.
     
  20. Alec_t

    AAC Fanatic!

    Sep 17, 2013
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    As Crutschow says. Give the non-inverting input somewhere for a finite input bias current to flow.
     
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