Implementation of NAND gate

Discussion in 'Homework Help' started by s3eng, Oct 3, 2015.

  1. s3eng

    Thread Starter New Member

    Oct 3, 2015
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    0
    hey guys i dont understand how this implementation of nand gate works...
    I can understand this,
    [​IMG]
    However i am having trouble understanding the logic behind the implementation of the NAND gate. According to the circuit on the left shouldnt
    Y's output be 0 when A AND B is 0? I know for NAND gates 0 and 0 is 1. However i dont undestand how the circuit diagram on the left works (means not the truth table and the NAND gate diagram on top of the table).

    [​IMG]

    Please help thanks.
     
  2. Jony130

    AAC Fanatic!

    Feb 17, 2009
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  3. WBahn

    Moderator

    Mar 31, 2012
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    Neither one of your images is displaying. Please upload them to the AAC server as either an attachment or embed them in your post. Please make sure they are reasonably sized (100 kB is MUCH preferred over 1 MB).
     
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