question: implement a 4 bit ring counter using ACTEL FPGA with optimized number of logic modules (ACT 3)
this is my approach. kindly guide me
i believe that there should be four act 3 s modules one for each bit. i am not sure about the interconnects. in a ring counter if the input is 0001 the output should be 0010 right. if my bits are q3 q2 q1 q0, q3 being my most significant bit, should i connect the output of the logic module implementing q3 to multiplexer of the act 3 module producing q0.
I've attached a picture of what i think might be the solution.

kindly help me.
thanks

 

You question is wide and, frankly, rambling.

Are you asking what a ring counter is?

Are you asking how to implement a ring counter?

Are you asking what an "act 3 s" module is?

How are we possibly supposed to decipher anything from your diagram. You have some unnamed block that apparently has six unlabeled inputs and one unlabeled output.

You have a bunch of two-input AND and OR gates, each with a HI (a 1) going to both inputs. What purpose are they supposed to be serving?

You need to do a much better job of coherently describing your problem, your resources and constraints, and your efforts to date.

 

thanks for the suggestions. i'm a college student and am still learning.

my question is how do we implement a 4 bit ring counter using act 3 sequential modules.
i have a solution to the question but i'm not sure if its right. i need some guidance.
i have made another picture which is hopefully more clear. i have 4 act 3 s modules each implementing one bit. q3 is the most significant bit and q0 the least. an act 3 s module consists of 4:1 mux whixh is connected to a d flip flop. the two select lines of the mux are connected to an 'or' and 'and' gate. supposing the select lines are s1 and s0. i've given a high or '1' to both the inputs of the and gate to make s1 = 1. as for the or gate i've given q2 and 0, for the s module implementing bit q3. i want the output of the of this module to be q2. so when q2=0, s1s0= 01, selecting the second pin of the mux. the output of this module would be 0 in my figure. if q2 =1 then pin 3 would be selected and the output would be 1. the remaining three s modules work in a similar manner. so id the present state of q3q2q1q0 is 0001 the next state would be 0010.
i've also attaches an image of a act 3 sequential logic module for reference.
is my approach correct?
thanks

 

That's a much better description.

What are the inputs to each of the four data inputs of each MUX. Your diagram just has them floating.

How do you initialize/reset the counter?

 

Another thing to keep in mind is that the problem asks you to use an "optimized" number of ACT 3 s modules. You are using four.

How many total states are there?

How many bits of state are required to represent that number of states?

 

the inputs to the muxes are 0, 0, 0, 1 for pin 0, 1, 2, 3 respectively. its the same for all the logic modules. the truth table of a ring counter is as shown below

(present state) (next state)
q3 q2 q1 q0 q3+ q2+ q1+ q0+
0 0 0 1 0 0 1 0
0 0 1 0 0 1 0 0
0 1 0 0 1 0 0 0
1 0 0 0 0 0 0 1
so basically, q3+ = q2
q2+ = q1
q1+ = q0
q0+ = q3

i dont think we have to bother about the states in this question.

so i want the output of the logic module implementing bit q3+ to be q2... thats why i have designed the 4:1 mux as shown in the picture. the same goes to the other modules. i'm not sure how to set or reset the flip flop. as for the number of modules, i think it should be four because this problem was solved partially in my class and they used four modules. one module for each bit.

 

spaces in the truth table disappear once you post the reply. looks a little messy...

 

Look at using the TABLE tag to make your tables more presentable. It doesn't do everything that would be nice, but it makes basic tables a lot more readable.

i dont think we have to bother about the states in this question.

Not if you are okay with using 4 s-modules. Now, if someone else does it with 3 and someone else does it with 2, how much credit should using 4 get when you are supposed to optimize the number of s-modules?

So please answer the questions I asked before. How many different states do you need and how many bits of state information are needed to represent them?

so i want the output of the logic module implementing bit q3+ to be q2... thats why i have designed the 4:1 mux as shown in the picture. the same goes to the other modules. i'm not sure how to set or reset the flip flop. as for the number of modules, i think it should be four because this problem was solved partially in my class and they used four modules. one module for each bit.

So what if the circuit powers up all 1s? All 0s? Two 1s and two 0s?

If it powers up in ANYTHING other than exactly one 1 and three 0s, you are screwed. What do you think the chances are of it powering up with exactly one 1 and three 0s? So perhaps it is something that should be considered.

 

ok so thats the state diagram right? so there must be four states.
state a - 00 (0001)
state b - 01 (0010)
state c - 10 (0100)
state d - 11 (1000)
so i would need two bits to represent the states.

 

maybe i should preset the d flip flop in the logic module implementing bit q0 and clear the rest? preset and clear both are active low. so i should send a low to the preset. and a low to the clear of the remaining flip flops. so initial state would be 0001. after that i would get 0010. is that right?

 

ok so thats the state diagram right? so there must be four states.
state a - 00 (0001)
state b - 01 (0010)
state c - 10 (0100)
state d - 11 (1000)
so i would need two bits to represent the states.

Correct. So this machine can be implemented using only two s-modules.

 

maybe i should preset the d flip flop in the logic module implementing bit q0 and clear the rest? preset and clear both are active low. so i should send a low to the preset. and a low to the clear of the remaining flip flops. so initial state would be 0001. after that i would get 0010. is that right?

Now you seem to be switching back to a four-bit solution. If you have a two-bit solution, then all four possible states are valid states in your machine, so it has no choice but to power up in a valid state. So unless you need to be able to reset it to a particular state, you can let it power up wherever. If you do need it to reset to a particlar state, then you can simply have it reset to the all-0 state and just decode that state as the one you need it to be.

 

k i got it...thanks for the help!