I have a quick question. I'm currently trying to implement a J-K FF using a DFF. I have the graphic representation of the circuit, and I'm just having trouble trying to implement it into a logic diagram on LogicWorks 5.

Function table:

This is the graphic representation:

And this is my logic diagram:

Is my logic diagram correct?

 

Your analysis is correct up to the point where you try to implement it with an IC.

Inputs J and K are asynchronus inputs that don't need to be fed anywhere else but in the Logic Gates circuit you have built in in the image second to last.

The 74175 IC has 4 D-FFs in it. You need to use only one. So take the circuit you built in the second-to-last image and connect the D output of the OR gate to one of the inputs of the 74175 (i.e. pin #4) and you will take the output of the FF, Q, from the corresponding outputs (i.e. pins #2,3).

Is that clear?

 

Okay I think I understand now.

Is this what you mean?

Also, is the clock and +5V connected correctly to the '175 device? And is it normally necessary to have those binary switches?

 

This is correct. However, you don't need an inverter to complement Q. You already have Q' ready from pin 3 of your IC.