Impedance matching in PCB design

Discussion in 'General Electronics Chat' started by Narwash, Aug 24, 2012.

  1. Narwash

    Thread Starter Member

    Jun 27, 2012
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    Hi all,

    I'm designing an amplifier on a PCB, doing it myself with just some FR4 boards. I was wondering how careful I should be about impedance matching along traces. Should I be really strict and maintain a constant trace width everywhere, or is a variation of about .5mm going to cause reflections and such. My traces are about 1.01mm wide but go up to 1.25mm in some places. I'm just worried that I'm going to run into oscillation unless I keep a uniform trace width.

    In addition, how strict are ICs in impedance matching? I can't seem to find documentation on the IC datasheet on the functionality of the chip if it isn't matched to a 50 ohm trace or anything.

    If anyone could link to impedance matching in PCBs documentation/guides, I would appreciate it.

    Thanks for your help!
     
  2. crutschow

    Expert

    Mar 14, 2008
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    You only need to worry about trace impedance matching at high frequencies, where the propagation delay of the trace length becomes a significant fraction of the waveform time period for one cycle of an RF signal or a significant portion of the rise-time for digital signals.
     
  3. Narwash

    Thread Starter Member

    Jun 27, 2012
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    Ah yes that's right. My maximum operating frequency is 50 MHz. Is the idea that if my trace lengths are about 1/100th of a wavelength I would need to include impedance matching considerations in my design? A 50 MHz signal has a wavelength of 6m. Would my traces need to be 60mm long for impedance matching considerations to come into play? Or is there some other considerations I'm missing. Maybe I don't need to worry about it too much unless I'm in the gigahertz range. Thanks for your help!
     
  4. Ron H

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    Apr 14, 2005
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    A quick simulation tells me that a 200pS, 50Ω line, with zero source impedance and 1Meg load impedance (in other words, severely misterminated on each end) would have 0.017dB peaking at 50MHz. A 500pS, 50Ω line would have 0.107dB peaking.
     
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  5. crutschow

    Expert

    Mar 14, 2008
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    A more typical rule-of-thumb for most applications is to consider it a transmission line when the length is greater than 1/10 of the wavelength.
     
  6. Ron H

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    I think it depends on whether your circuitry is analog or digital. If it's digital, overshoot and ringing are the primary deciding factors. If it's analog, then the critical length depends on how much VSWR, etc., you can tolerate.
     
  7. crutschow

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    True. With digital it's the risetime (which has high frequency components) not the digital frequency that is the determining factor. I've seen a rule-of-thumb of 1ns of risetime per inch of line for the point at which the line should be considered a transmission line. Thus for a 10ns risetime (or falltime) the line could be up to 10 inches before you should be concerned.
     
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  8. Narwash

    Thread Starter Member

    Jun 27, 2012
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    Thanks for your thoughtful replies Ron and crutschow! I appreciate it. I have some additional questions though.

    What simulation software did you use for this? And the 200pS is the propagation delay of the line, correct? Did you derive this from inductance and capacitance per unit length of an FR4 board? Or were these numbers just chosen to show that even in the extreme case, minimal peaking occurs due to the transmission line.

    Oh and this board is all analog so I don't need to worry about digital considerations right now.

    Thanks again!
     
  9. Ron H

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    I ran the simulation on LTspice It is used by many electronics hobbyists (and professionals). It is free, and is well supported, including an active Yahoo group.
    As with most circuit simulators, it includes a lossless transmission line model. I used this in the simulation. It also has a lossy tline model, but the results for such a short line would typically be similar to a lossless line. "Short" is relative to the wavelength, in this case, 1/100.
    Yes, 200pS is the propagation delay of the line. The dielectric is irrelevant. The same results will occur with any (lossless) 200pS line. No calculations involving L and C were used.
     
  10. Narwash

    Thread Starter Member

    Jun 27, 2012
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    Thanks Ron! I use LTspice as well and I'm liking it so far. Now I can direct all my LTspice questions to the yahoo group as well.

    I suppose my question is, how do you know that the line has a 200 pS propagation delay? From wikipedia I found this statement "Wires have an approximate propagation delay of 1 ns for every 6 inches (15 cm) of length". Is this an accurate rule of thumb? Or does this apply more to digital circuits? If it is correct, I would need a 30mm line to get 200 pS of propagation delay. I'm assuming that since both FR4 traces and wires are ideal conductors, the same rule applies to both. I'm just trying to figure out where the 200 pS propagation delay is derived from.

    Thanks for all your help!
     
  11. Ron H

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    Place a tline on your schematic. You will see that Td is an editable parameter. The physical dimensions are irrelevant to a simulation.
    Light travels at about 1nS/foot. The propagation velocity of a transmission line is inversely proportional to the square root of the dielectric constant that the line is imbedded in (assuming a surrounding ground return).
    The dielectric constant of FR4 is around 4.5, ± a few tenths, depending on mfr and batch.
    This means that the prop velocity of imbedded stripline (ground on both sides) is about c/√4.5, or a little less than 6"/nS.
    For microstrip (surface trace over ground) on FR4, the effective dielectric constant is less than that of FR4, because air is the dielectric on the other side).
    As I said before, I chose 200pS because it is 1% of the wavelength of 50MHz, which you mentioned in post #3.
     
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