IF signal amplify without delay

Discussion in 'General Electronics Chat' started by himadri117, Nov 12, 2014.

  1. himadri117

    Thread Starter New Member

    Nov 11, 2014
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    I have a RF Frontend that has an 4 IF signal output (2 I channel and 2 Q channel from 2 receiving anettans). Each channel of the IF has a signal rangining from 1.5V to 3.5V with a DC offset of 2.5V.

    IF output signal: (http://tinypic.com/r/2gx2zd1/8)

    I want to sample the signal with an ADC that has a reference voltage from 0 to 5V and use the mid range of 2.5V for better sampling.

    So,I prefer to shift the signal and amplify to make it from 0.5V to 4.5V with a offset of 2.5V.

    Desired output signal(http://tinypic.com/r/2cmvkt4/8)

    I tried coupled capacitor then level shift and gain with op-amp, also other shifting circuit, but the coupled capacitor to block the DC causes a little phase shift which is not desireable. So I don't want to filter the DC and aamplify to my desired signal. Please suggest me a circuit that will work without delay and phase shift.
     
  2. Papabravo

    Expert

    Feb 24, 2006
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    Wouldn't it be better to sample the signal directly if your main concerns are delay and phase shift. If 6 dB of gain is important and you apply the same delay and phase shift to both I & Q, what have you lost?
     
  3. alfacliff

    Well-Known Member

    Dec 13, 2013
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    the delay and phase shift will not matter if you use two if amplifiers that are identical. same phase shift and delay in each.
     
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  4. crutschow

    Expert

    Mar 14, 2008
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    Use a larger capacitor.
     
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  5. alfacliff

    Well-Known Member

    Dec 13, 2013
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    usually for an I Q type reciever, the dc componant of the i and q are ignored as a leftover from the mixer. and the I and Q signals are sent to seperate amplifiers till they get to the demodulator circuit. if the seperate amps are identical, the phase relationship is maintained.
     
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  6. himadri117

    Thread Starter New Member

    Nov 11, 2014
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    Thanks for the reply. So you say I should filter out the DC using a coupled capacitor?
    In that case there is no DC off set and I have the signal (with less than 2V peak to peak) going in the negative which is not good for the ADC. I simulated in spice shifting the voltage. But with my design I'm not able to get a signal from 0.5v to 4.5v with DC offset 2.5v... which would be a ideal case for sampling.
     
  7. himadri117

    Thread Starter New Member

    Nov 11, 2014
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    It is possible to sample the signal directly, but I"m trying to achieve the signal from 0.5v to 4.5v by shifting and amplifying.
     
  8. Papabravo

    Expert

    Feb 24, 2006
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    Why not run the processor with the A2D from ±2.5V supplies?
     
  9. himadri117

    Thread Starter New Member

    Nov 11, 2014
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    The ADC has no negative reference, only from 0 to 5V
     
  10. Papabravo

    Expert

    Feb 24, 2006
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    As I understand it the processor has an internal ADC. If Vss = -2.5V and Vdd = +2.5V, it means tha Vdd - Vss = 5V !! What is the problem with the reference? The range of the reference is -2.5 to 2.5 and you can use GND as the middle of the range.

    It might help if you could give us a schematic with some part numbers instead of forcing us guess about everything.
     
  11. AnalogKid

    Distinguished Member

    Aug 1, 2013
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    You have two sources of delay. The amp delay probably is not frequency dependent unless you are pushing the gain-bandwidth curve. The coupling capacitor delay is freq dependent even if the corner frequency is several decades away from the frequency of interest. What about summing in a DC current to get the offset you want? That would eliminate the coupling cap problem. For the amps, go with a dual or quad amp chip to get the best performance matching.

    ak
     
  12. himadri117

    Thread Starter New Member

    Nov 11, 2014
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    So here is a LT spice circuit I made to level shift after removing the DC offset.

    http://tinypic.com/r/24aye60/8

    The signal has very low amplitude now.Can you suggest a circuit to keep the DCoffset at 2.5V andamplify the signal from 0.5v to 4.5V?
     
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