Hi guys,

i searched the forum for about 15 minutes and didnt find any discussion on this topic.

Can anyone link me to a microchip app note regarding an example ICSP circuit, or at least, a discussion about whats really required for the hardware aspect.

I am working on an 8-page schematic at work and i would really like to avoid reading/skimming hundreds of pages of app notes if possible.

thanks,

Dan

 

The Microchip manual is called: In-Circuit Serial Programming™
(ICSP™) Guide

It is quite lengthy, or I would attach the pdf. Which chip are you using? There are shorter, chip-specific sections.

John

 

Hi.

Is it for a specific PIC, or more in a general manner?

This is a circuit, with ICSP, for the PIC 16F628. LED is connected to RB0. So is the top pins in the upper left corner.

More pictures in my album...

 

I designed a poster for ICP PIC programming.
http://www.blueroomelectronics.com/downloads/Hello%20World%20%20Project.pdf

 

nice guys, thanks a lot.

i am still waiting on my manager/software developer to pick the exact device - but i think its going to be a 16 I/O count PIC.

i had quickly read something about isolating a Vpp (?) voltage and signals during programming and regular operation if you were sharing them and it just seemed like things could quickly get overly complex if i didnt follow some quick quideline from microchip.

i think with the 16 I/O count we wont be sharing the programming lines, so the circuit should be relatively simple.

thanks for the links!

-Dan

 

Hi
Also take a look here. It is quite well explained. The tips will be valid for most ICSP programmers
http://ww1.microchip.com/downloads/en/DeviceDoc/51764C.pdf

 

nice, thanks again

found out the device we will be using is the PIC12F629. It simply functions as an interlock monitor and locks out the enabling of some high voltage (15kV) biasing supplies until the high level software has re-requested the high voltage.

 

The 12F629 only has 5 I/O & 1 input pin. You have to be very careful to keep the PGC,PGD,VPP free from low impedance circuits.

 

The 12F629 only has 5 I/O & 1 input pin. You have to be very careful to keep the PGC,PGD,VPP free from low impedance circuits.

Perhaps the OP meant 16f629.

 

If all else fails you can use jumpers and remove them to program the chip.

 

we only need 3 I/O pins

its a very simple single process micro - simply latching an enable line based on the status of 2 signals - an interlock and the CPUs request for high voltage.

it is meant to protect from rapid restoration of 15kV during an interlock removal and re-insertion.

the "conditioned" enable signal feeds a CPLD which does a switching algorithm/state machine for polarity switching.

originally we had the CPU enable going to the CPLD, but the CPU does not deassert the line on an interlock violation - this signal is not connected to the CPU, which is a single board CPU (for now).


in order to ensure safety, we are now polling the interlock status to lock the enable signal going to the PLD after an interrupt, until the CPU re-requests the supplies be enabled. The CPU also now, has "eyes" to the interlock status.

hope that explains, its somewhat convoluted and i think i rambled while typing...