IC tristate I/O question

Discussion in 'Homework Help' started by sungchoiok, Jul 15, 2011.

  1. sungchoiok

    Thread Starter New Member

    Apr 23, 2011
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    Hello. I need some help with configuring tristate input/outputs for ICs.

    This is a hypothetical RAM. It has two address inputs, three control lines, and one-bit I/O bus. Now, I understand how to use pull-up resistors to send signals to the input pins, such as the /WE, /OS, /CS, A1, and A2 (as shown on the first thumbnail), but I do not understand how to configure my circuitry so that the I/O bus gets input signals, but also output a signal when it is requested to.


    To explain again... the I/O pin receives an input when the chip is writing, and outputs a signal if it's reading. How would I render the circuit so that both are available?


    the second thumbnail shows the solution I thought about--probably looks ridiculous to a person who actually knows what they are doing :(



    thank you so much
     
  2. Georacer

    Moderator

    Nov 25, 2009
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    1,266
    Usually the data I/O bus is multiplexed or the pins that can "see" it do so through a tri-state buffer.

    That means that you can switch which pin will see the I/O pin each time and thus select between input or output pins from your uC or processor.
     
  3. sungchoiok

    Thread Starter New Member

    Apr 23, 2011
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    I hope I'll get this right the first time--is it?

    [​IMG]



    p.s. I'm really sorry for the crude pictures.
     
    Last edited: Jul 16, 2011
  4. sungchoiok

    Thread Starter New Member

    Apr 23, 2011
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    I did some more research and updated my new schematic above.
     
  5. MrCarlos

    Active Member

    Jan 2, 2010
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    Hello sungchoiok

    In Your hypothetical RAM sometimes you have to read from the "Memory", sometimes We have to write it.

    So when you read from it, this is programmed as output. and when you write it is programmed as inputs.

    It's as if the terminal I/O had a 1-pole 2 position switch SPDT.

    Assuming that our RAM, to store, has a D-type Flip-Flip
    To record the D would be connected to the I/O terminal.
    Reading the Q would be connected to the I/O terminal.
    That would make it through the SPDT switch.

    Indeed it is used instead of the SPDT switch transistors like: CMOS, FET's, MOSFETS Etc.

    This switch is managed with the control input named WE.
    If "WE" is true we are writing. But if “WE” is false we are reading.

    Greetings
    at your service
     
  6. Georacer

    Moderator

    Nov 25, 2009
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    What's the purpose of the circuit from the ULN2003 and below? If it's the external reading module, you might think about isolating it too, as you might not want it to read what you write in the RAM everytime.

    The use of the tristate to isolate the write input is correct.
     
  7. sungchoiok

    Thread Starter New Member

    Apr 23, 2011
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    thank you for the kind answers

    MrCarlos--I don't know if I understood incorrectly, but the WE line is actually negated; so when I send a signal to that pin, it's reading--otherwise, writing.


    Georacer--I will do that--separating the reading module. As for the ULN, I was thinking of driving a small 5V relay from the IO pin (please don't ask me why lol)

    As for the resistors, about 10K Ohms is one-size-fits-all for 5V CMOS ICs, right?
     
  8. Georacer

    Moderator

    Nov 25, 2009
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    Check the minimum input current to be sure. You don't want your input to starve. Can't harm you being a bit too cautious.

    Your inputs don't run a risk from being connected directly to the 5V (the logic gates at least, I don't know about the RAM), but you don't want your pull up resistor to degrade into a short circuit.
     
  9. sungchoiok

    Thread Starter New Member

    Apr 23, 2011
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    Ok. Thank you so much for all the help :)
     
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