I just don't grasp what you guys are communicating...

 

So, even if all the gates were on separate chips, I would still get this problem?

 

A gate outputs a high voltage because it closes a switch between the output pin and Vcc.

A gate outputs a low voltage because it closes a switch between the output pin and GND.

Now close both switches at the same time.

Poof! You've let the magic smoke out!

 

I feel like this is a simple concept, but It's just going over my head. Perhaps a simple diagram would help?

 

Here is what a 7400 TTL gate looks like internally. Ignore the left drawing and focus on the right hand drawing. This is a simple model of how the output transistors operate.

When the gate wants a HIGH output, Q4 conducts and Q3 is open.
When the gate wants a LOW output, Q4 opens and Q3 conducts.

Now imagine that you connect the output of another gate to this output. It does not matter where that gate is. It can be on a different chip on a different board.

If Q4 of one gate and Q3 of the other gate are both closed, this is a short circuit across the power rails and the high current can fry your chips.

 

In addition to the problem of tying the outputs together, resulting in hitting the package limit for I/O current sinking and sourcing to itself, and the other issues and questions above...

When working with logic, always remember to add a 0.1uF cap between Vcc and GND on the IC itself. With breadboards in general, I put a 22uF cap on each rail, then a 0.1uF every 15 rows or so on each side (min, 1 per side) in addition to a 0.1uF cap across each IC. Breadboards are VERY noisy, and the bypass caps help reduce odd glitches with circuits that switch quickly. These are a permanent fixture on all of my breadboards with logic, microcontroller, and analog circuits due to the number of headaches saved.

With your circuit above, something like a diode-OR between your inputs and the Inputs/outputs of the switches and inverter (thus avoiding shorting the IC outputs together). The unused inputs should also be either tied to Vcc or GND through a resistor, rather than left floating. Floating inputs can result in the IC oscillating on it's own (which stops when probing to find the problem due to the added load)

 

Here is what a 7400 TTL gate looks like internally. Ignore the left drawing and focus on the right hand drawing. This is a simple model of how the output transistors operate.

When the gate wants a HIGH output, Q4 conducts and Q3 is open.
When the gate wants a LOW output, Q4 opens and Q3 conducts.

Now imagine that you connect the output of another gate to this output. It does not matter where that gate is. It can be on a different chip on a different board.

If Q4 of one gate and Q3 of the other gate are both closed, this is a short circuit across the power rails and the high current can fry your chips.

That make it so much clearer! Thank you for the explanation! Now, that is only TTL right, does the same apply to CMOS?

 

In addition to the problem of tying the outputs together, resulting in hitting the package limit for I/O current sinking and sourcing to itself, and the other issues and questions above...

When working with logic, always remember to add a 0.1uF cap between Vcc and GND on the IC itself. With breadboards in general, I put a 22uF cap on each rail, then a 0.1uF every 15 rows or so on each side (min, 1 per side) in addition to a 0.1uF cap across each IC. Breadboards are VERY noisy, and the bypass caps help reduce odd glitches with circuits that switch quickly. These are a permanent fixture on all of my breadboards with logic, microcontroller, and analog circuits due to the number of headaches saved.

With your circuit above, something like a diode-OR between your inputs and the Inputs/outputs of the switches and inverter (thus avoiding shorting the IC outputs together). The unused inputs should also be either tied to Vcc or GND through a resistor, rather than left floating. Floating inputs can result in the IC oscillating on it's own (which stops when probing to find the problem due to the added load)

Can you further explain that cap concept please?

 

That make it so much clearer! Thank you for the explanation! Now, that is only TTL right, does the same apply to CMOS?

Yes, the same applies to CMOS.

 

Yes, the same applies to CMOS.

So, how can I change my circuit to fix this?

 

Can you further explain that cap concept please?

Click on "Bypass caps, Read Me!" in sigline. I only mention it as secondary information to your primary issue due to the number of times an unstable supply ends up causing problems.

 

So, how can I change my circuit to fix this?

If you have some diodes on hand, connect a diode in between your output and where the outputs meet(right now)...

 

So, how can I change my circuit to fix this?

See This post from This OLD thread, don't bump that thread, keep the discussion here.

The post I linked from Ron H shows how to wire a diode AND gate without using another IC.

 

See This post from This OLD thread, don't bump that thread, keep the discussion here.

The post I linked from Ron H shows how to wire a diode AND gate without using another IC.

Sorry, I didn't quite understand that.

 

Sorry, I didn't quite understand that.

How to make a Resistor-Diode AND gate to combine two IC outputs, without damaging either IC output.

The thread is a topic on a combination lock, which looks like what you are trying to build, so if you read the full thread, rather than that excerpt post/image, it may make more sense.

 

If you learn some more about the logic families, it will help you to handle the logic circuits.

Logic Families 1, Logic Families 2, DTL.

 

Don't know if I have this right. I need OR gates?

 

You can make AND gates as well as OR gates with diodes and resistors external to your IC.

You showed a diagram above with all of the outputs tied together. You assumed that "high" outputs would "overpower" low outputs (an incorrect assumption).

If you start from scratch, and explain what you are trying to accomplish, without bringing ANY details of the existing (non-working) circuit into the description, that may be the best approach to decide what you actually need to accomplish what you are trying to do.

It boils down to this:
1) Supply: +5V
2) Inputs: ???
3) Output(s): ??

If you only have one output, how should it respond? If you have multiple inputs, what needs to be unique about them to give the desired output? Use plain English description, just like this paragraph. You don't need to mention gates, ICs, LEDs or any type of component to explain what you are trying to do, though you can indicate you'd like a light on or off.


Just a description like:
"When switches w, x, y, and z are on, the output is high. If any other switches are on, the output is low, even if w,x,y, and z are on". That's all that is needed to walk you through the rest of the process to decide what parts to put into your circuit.

 

Very well.

I wish for the primary output (The one connected to the LED) to always be low, unless switches 1, 2, 4, 5, 8 are all high, and switches 3, 6, 7 are all low. Any other combination of these switches, no matter how insignificant, will result in a low output.

 

Connect 3, 6 and 7 to individual inverter gates.
Then connect all eight signals via eight diodes as shown in the example above.

Or you can use a single 8-input AND gate.