I-V Characteristics (Curve Trace) - FET

Discussion in 'General Electronics Chat' started by Management, Mar 31, 2009.

  1. Management

    Management Thread Starter Active Member

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    Hi, does anyone know how I can get a I-V characteristic of a FET in PSpice? Basically the same thing a curve trace would give you.

    If that isn't possible, how can one confirm some of the specs on a datasheet.

    Basically I would like to test how a particular model is operating. What specs should I be focusing in, Vth, Idss, Drain Source Voltage and Current, Vgs voltage characteristics, etc?

    Thanks in advance.
  2. Ron H

    Ron H E-book Developer

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    I can show you how to do it in LTspice. You could probably easily translate that into Pspice. Let me know if you want to see it.
  3. Management

    Management Thread Starter Active Member

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    Yes please show me. I also have LTspice installed but I think I would be able to translate it because I am more comfortable with Pspice than LTspice. Either way should work for me though.

    Thank you so much.
  4. Ron H

    Ron H E-book Developer

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    It's just nested DC sweeps of Vds and Vgs. If you save the .asc file in the location where your other LTspice sims are located, you can then start LTspice and run this sim. Right-click on the .dc directive to see the source sweep parameters.
    If you don't have a model for 2N4416, pick another model.

    Attached Files:

    SiegeX1 likes this.
  5. Management

    Management Thread Starter Active Member

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    Your the best. Thank you very much.

    Also, is it possible to do a CV curve in PSpice or LTspice? Would I just do a DC Analysis and sweep the gate while shorting the drain and source to groung? If so, how would I plot the high frequency curve and low frequency curve?

    Thanks again.
  6. Ron H

    Ron H E-book Developer

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    I used to run CV sims on MOSFETs when I worked at Micron. The principle is fairly simple:
    I=C*dv/dt
    C=I/(dv/dt)
    For a reverse-biased junction, or a MOSFET gate, apply a ramp (dv/dt) to the gate. You have to be judicious about the choice of dv/dt. First, choose a slope like 1e6 v/sec, or 1e3 v/sec, so that the capacitance is in uF or mF.
    If you choose 1e12, and the capacitance is a few pF, you will get a few amps of current, which will cause series resistance in the model to be significant, screwing up your results.
    If you choose a slope that is too slow, like 1 v/sec, the current will be so low that leakage current will be significant.
    You can see Miller capacitance with this technique, as in the attached simulation. I added known values of R and C as a sanity check.
    Obviously, you can change Vds or Rd, depending on what you want to measure. You will have to change the amplitude of the gate ramp to accommodate devices with different Vgs(th).

    Attached Files:

    SiegeX1 likes this.
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