# I thought high FET gain was not possible, but...

Discussion in 'The Projects Forum' started by Darkstar, Jun 30, 2011.

1. ### Darkstar Thread Starter Active Member

Sep 3, 2010
104
0
I've been playing around with circuit simulations to tweak variables and I've gotten signal gains as high as 23 with these FET circuits (signal out/signal in). I didn't think gain like this was possible for a simple FET circuit. I've attached a graph of my results and a table of the data.
Can someone tell me if this data is correct or just a fluke of the website calculations somehow?
Thanks

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2. ### InnocentOfTheWorld Member

Apr 15, 2010
47
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rather than reading on websites i suggest you sedra and smith you will gain good concepts.
without looking at the circuit to which you are feeding input and configuration it's hard to answer

3. ### Darkstar Thread Starter Active Member

Sep 3, 2010
104
0
Here's the circuit that gave me the highest gain (23.07).
power=30V
Top resistors=9K
Top 2 pots are each 1K with a 767 - 233 ohm split
FETs have a Vp = -8 V
Bottom pot in bridge is 10 ohms with 1 ohm jumpers on each half to keep resistance low but allow bridge output zeroing.
Last pot is 2K with a 1356 - 644 ohm split
Graphs show the input signal (1 mV) and the bridge output across the 10M resistor in the bridge (simulating a DVM)

When things are tweaked just right, the gain (signal out/signal in) is very high, though the calculated FET gain is in the normal range around 3 to 4. At these extremes, the bias resistor settings are very touchy. Sometimes just moving the pot one more "notch" on the simulation can send the output signal from the mV range down to the uV range. I'm wondering if maybe the high gains shown are just a fluke of working at these extremes. Maybe the calculations done by the website aren't completely accurate.

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Dec 26, 2010
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It looks likely that your FETs are on the point of running out of VDS. Up to a point, larger drain load resistances and larger gm (which generally goes with larger drain current) increase gain.

However, if you try to be too "greedy" with your high gain design, the DC conditions can become unsuitable. If the drain currents get too big, the difference between the drain and source voltages will be too small, and the amplifier will no longer work.

5. ### Darkstar Thread Starter Active Member

Sep 3, 2010
104
0
I think I understand now. I want good Ids, but not too much, and low Vds, but not too low.
Looking at my table, this info appears to point right to where gm and signal out amplitude are equal at about 4.1.
On one side, the signal amplitude is high vs gm and on the other side amplitude is low vs gm.
So, it seems the place to shoot for is about gm=4.1, Ids=-6.6mA, and Vds=-3.6V (at least in this circuit.)

Thanks, now I know what to adjust for and why.

6. ### Ron H AAC Fanatic!

Apr 14, 2005
7,050
657
Your data doesn't make sense. Negative values of Vds are not possible. The drain will always be more positive that the source. Furthermore, most of your Vgs values are greater (in magnitude) than Vt, which I assume is the cutoff voltage. Cutoff voltages in JFETs are typically measured at a very low value of Ids, like 1nA.

EDIT: I just noticed that your Ids values are also negative.

7. ### Darkstar Thread Starter Active Member

Sep 3, 2010
104
0
I'm just reporting the values as given to me by the website. It does the calculations. The schematics posted are screenshots. The FET parameters are in the lower right corner and Ids, Vgs, and Vds are all given as negative values. If I connected the polarity in reverse, the circuit would not function. These do.