# I have confusion about biasing circuit to FET (Field Effect Transistor) amplifier.

Discussion in 'General Electronics Chat' started by Dong-gyu Jang, Jan 31, 2016.

1. ### Dong-gyu Jang Thread Starter Member

Jun 26, 2015
100
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Hello.

Please see the following images.

This is JFET amplifier.

And this is only biasing circuit to the amplifier.

Let's say V_DD is 12 V and R1 = R2 = 1 kΩ. Without V_IN, V_G is clearly 6 V, no doubt at all. good.

However, when V_IN applies, how can I determine V_G? Some signal current from V_In should flows along the path from + GND through C1 and R2 so that current times R2 gives V_G. But...V_G is also determined as 6 V from voltage divider. This is contradiction and if V_G is fixed, whole circuit means nothing to do useful job.

There is something I can't see right now. Could you please fix my vision to this circuit?

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2. ### David Knight New Member

Aug 4, 2015
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3. ### Jony130 AAC Fanatic!

Feb 17, 2009
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5. ### crutschow Expert

Mar 14, 2008
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Assuming C1 is large enough to have an impedance much smaller than the parallel value of R1 and R2 at the input frequency, then Vg will be the DC bias (6V) plus and minus the input AC voltage.

6. ### Dong-gyu Jang Thread Starter Member

Jun 26, 2015
100
4
Hello.

I think C1 can be fairly small as DC biasing current from VCC power source will not enter even with small C1, biasing voltage is still 6 V.

7. ### Alec_t AAC Fanatic!

Sep 17, 2013
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Adding to Crutschow's contribution, if C1 is small it will have a high AC impedance so the signal will have only a small effect on the gate voltage.

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8. ### crutschow Expert

Mar 14, 2008
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Certainly the size of the capacitor has no effect on the DC bias.
But the capacitor has to be large to pass the AC voltage without significant attenuation.
The AC signal will be attenuated by -3dB when the capacitance reactance at the input frequency equals the parallel value of R1 and R2 and rolloff at -6dB/octave below that frequency.

Since the purpose of this circuit is to amplify AC signals, you don't want to attenuate the AC input signal.

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9. ### hp1729 Well-Known Member

Nov 23, 2015
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Not homework, right?

VGS of 6 Volts? Or <0.6 V including signal. Should you avoid forward biasing the gate? It will be conducting as VGS gets down to about -0.7 V. The more negative VGS the more the JFET turns off. Depletion mode device, right? As voltage is applied to the gate it turns off.
6 V on the gate, yes, as long as > 6.7 V is dropped across the Source resistor.
Jeeez, JFETs has been a long time ago for me.
(edited to correct my math and thinking)

So what kind of signal is being applied?

Last edited: Jan 31, 2016

Apr 5, 2008
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11. ### hp1729 Well-Known Member

Nov 23, 2015
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JFET exercises
One exercise is just the JFET with a Drain resistor to +5 V. V in is varied and the output voltage is noted.
The other is similar to the circuit in this thread.
Included is the results in an Excel file (pdf format).

No, biasing does not have to be at 1/2 of VDD. Many examples are around with the high side resistor being a 220K and the low side being 22K. I have never done an exercise with this configuration.

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• ###### J107 12 V.pdf
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Last edited: Jan 31, 2016
12. ### hp1729 Well-Known Member

Nov 23, 2015
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So what happens if we change the voltage divider to 220K and 22K?

Our input voltage range shifts up.

Does this help the question about biasing point?

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