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i have a vhdl theory question wanna ask question

L

Thread Starter

longcrystal

Joined Mar 22, 2010
20
i got two question ...one is theory question and one is vhdl source code.

what is the advatange of the pdcpa alogirthm over the cpa alogorithm.??????????????



let say this source code are wrong i trying to correction , can some pro programmer??help me to see ..i correction the part correct???

entity
Type T_BYTE is array (7 downto 0) of std_logic;
Signal addit : std_logic_vector(7 downto 0) ;
Signal Type_byte : T_BYTE;
Signal Type_bit : bit_vector(7 downto 0);

Are the following signal assignments legal VHDL statements? If not specify how to make them valid.
Type_bit<= addit;
Type_byte<= addit;






i try to correct at this part ..can i do like this ???i try to modify and make that valid condtion . but i am not sure i doing correct or not..just need some ppl help me to verify it.

type_bit<=addit(bit_vector(7 downto 0));
Type_byte<= addit(T_BYTE);
 
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