I'm newbie with max+plus II and digital modelling world just want to simulate a simple ring counter

the ring counter must have initial value 1 (input port A) so I could not delete input A
as you see the output of dff #3 is connected to the input of dff #0
I keep getting this errorutput Q and input A are tied together
ring counter gdf file:
https://www.dropbox.com/s/y4zp8x6q5o9uf1y/ringcounterdff.gdf
thanks

 

Output Q3 and Input Vcc both are voltage sources, and the simulator correctly sees this as an error. You have the Q3 output tied directly to the rail, which would destroy an actual chip.

You need to add a gate to the first FF D input to combine the two sources as logic signals. An OR gate will do this, but that is only half of the problem.

For the ring to progress properly, the input to the first FF must be forced high (Vcc) only at the time of the first clock pluse. After that, it wants to be connected only to the Q3 output. One way to do this is to replace the OR gate with a 2-to-1 multiplexer, and add another FF that controls mux front of the first ring FF.

ak