R=2kohm, C=150pF, 8K ESD test

 

What is your question?

 

Well, I have a question: How do capacitors protect against ESD?

I can see how tying myself and the device I am working on to ground thru a, say, 100,000 ohm resistor - but how does a capacitor help?

 

The total charge of an ESD pulse is usualy fairly low, the capacitor on an input pin stores the charge, and because of the V=Q/C equation, the voltage is C times lower than it would be without a capacitor (the actual voltage of the pulse). The capacitor is charging from the ESD, and thus it will reach only Q/C volts when all the carge is transferred to the capacitor.

Also beware this method of protection doesn´t work when dealing with HV power supplies etc., where the stored charge is "infinite" because the supply (or arcing or anything generating the current) can supply its current for infinite amount of time, so the input get's above its voltage limit at some point.


And anyway, I have no idea what is the resistor supposed to do, because shenhome in his hasty wannabe-question forgot to tell us if it's in parallel or in series, and what is this all about. The 8K ESD test is allso weird, maybe the test is supposed to be conducted at temperature of 8K, and I would like to see him do that.

 

A cap as a low-pass filter? The high-freq pulse gets directed to ground??

OR, the MOVs in our circuits look somewhat like capacitors....

Just commenting,
--Rich

 

The total charge of an ESD pulse is usualy fairly low, the capacitor on an input pin stores the charge,

Yea, I missed the "IO" in his title and went right to ESD protection as in wrist-straps and grounded mats for SERVICING.

I didn't really READ the title.

 

That sounds more like input filtering than ESD protection. Need to see the component arrangement. 2K is too small for a charge bleeder, and 150pF is not large enough to pass much of a pulse.

 

Not foolproof, but better than nothing. I'm assuming a 2k series resistor followed by a 150p cap to ground, and the test voltage is 8 kV. I'm also assuming this test reproduces a particular standard, in which case the ESD pulse risetime, falltime and duration will also be specified.

The stray parasitics in the R and the C will limit the effectiveness of this circuit, for instance a 0.25 W axial resistor will have about 3 pF of stray capacitance across it, so this will form an AC potdown with the 150 pF cap, and about 2% of that 8 kV will get through. That's about 160 V. Additionally the C will have stray inductance in series with it, and that will further reduce the attenuation of HF spikes.

Lower the inductance of the cap by choosing a surface mount variety as physically small as possible (ideally 0402 or 0603) and use at least two decent vias to connect to a solid ground plane. SMT resistors have low capacitance, but beware of flashover due to the high voltage.

You can add some free inductance with square-wiggled PCB tracks, and if the net goes to a through-hole then the track can spiral in to this.

Pi filters, 3-terminal caps and common-mode chokes are expensive but effective.

 

Hello,

A lot of information on ESD and ESD protection can be found in the links of this page:
http://www.educypedia.be/electronics/esd.htm

Greetings,
Bertus