Hi,
I am designing an integrator which integrate part of a sine wave periodically, and then the integrated voltage is held on a capacitor through an analog switch. The schematic of integrator as below :
U1/R1/C1 forms the integrator, while the analog switch S3 sets the output of integrator to zero when closed. U3 is a buffer. The "set_to_zero" signal goes high periodically at 40kHz frequency, 10% duty cycle. So the integrator integrates its input waveform / set to zero output periodically at 40kHz. Simulated results as below:
red : set_to_zero
orange : input waveform, 10kHz/100mVpp sine wave
greed : integrator output
blue : hold the integrator output on a capacitor
My problem is, there is a transient peak on integrator output every time integrator is toggled from zero output to integrated output, the peak lasts about 2us
The peak somehow effects the integrated voltage of this circuit, the only thing I know for now is increasing the supply voltage of integrator(U1) could reduce the peak, but it is not good enough, I would like to ask for suggestions about this problem, thanks in advance.
I am designing an integrator which integrate part of a sine wave periodically, and then the integrated voltage is held on a capacitor through an analog switch. The schematic of integrator as below :
U1/R1/C1 forms the integrator, while the analog switch S3 sets the output of integrator to zero when closed. U3 is a buffer. The "set_to_zero" signal goes high periodically at 40kHz frequency, 10% duty cycle. So the integrator integrates its input waveform / set to zero output periodically at 40kHz. Simulated results as below:
red : set_to_zero
orange : input waveform, 10kHz/100mVpp sine wave
greed : integrator output
blue : hold the integrator output on a capacitor
My problem is, there is a transient peak on integrator output every time integrator is toggled from zero output to integrated output, the peak lasts about 2us
The peak somehow effects the integrated voltage of this circuit, the only thing I know for now is increasing the supply voltage of integrator(U1) could reduce the peak, but it is not good enough, I would like to ask for suggestions about this problem, thanks in advance.