Hi guys, can someone tell what the diagram mean in ADDR and DATA, I can understand the CLKIN diagram, but I don't have a clue of what are the other two mean.

or if anyone came across a timing diagram tutorial, can you share the link please, thanks a lot

Zhuhua

 

The ADDRess and DATA traces indicate where multiple address and data lines may change in relation to the CLKIN and where they must be stable. The dashed vertical lines indicate where ADDR and DATA is sampled (on the rising edge of CLKIN in this case.)

In your diagram, ADDR is stable until the rising edge of the 4th clock. The address lines are updated immediately after that (indicated by the crossing traces) and then are stable for the next 11 CLKIN rising edges after which they can change again. Presumably, this clocks in an 11 bit address. Similarly, the DATA is stable until the 10th CLKIN where it can change after the 10th rising edge of CLKIN then must be stable for the next 9 CLKINs.

I'm not sure what device you are using but those are the basics of it. This is not a particularly good diagram. A proper spec will include things like Data HOLD times (how long the addr/data must be valid after the last CLKIN edge) and Data SETUP times (how long the addr/data must be valid before the first CLKIN after a change).

 

This is a horrible diagram for even more fundamental reasons. Without knowing what it is trying to tell you (which is probably indicated in a figure caption or paragraph heading), you don't know how to interpret things. For instance, we don't know which, if either, in an input or an output. Are we writing someting into the part, or reading something out of the part, or what.

But even leaving all of that aside, it shows two transitions of the ADDR lines but shows a transition of DATA 6 clocks after the first and also 4 clocks after the second. Which is it? Six, or four?

 

so what do you mean by stable? do you mean there no change of state(high/low) during 11 CLKIN?

What should I search if I want to know more, I don't seem to get much from google about this, or maybe I am just using the wrong key words

Zhuhua

The ADDRess and DATA traces indicate where multiple address and data lines may change in relation to the CLKIN and where they must be stable. The dashed vertical lines indicate where ADDR and DATA is sampled (on the rising edge of CLKIN in this case.)

In your diagram, ADDR is stable until the rising edge of the 4th clock. The address lines are updated immediately after that (indicated by the crossing traces) and then are stable for the next 11 CLKIN rising edges after which they can change again. Presumably, this clocks in an 11 bit address. Similarly, the DATA is stable until the 10th CLKIN where it can change after the 10th rising edge of CLKIN then must be stable for the next 9 CLKINs.

 

so what do you mean by stable? do you mean there no change of state(high/low) during 11 CLKIN?

That's right. If it were a serial address, you would see ADDR change (traces cross) on every clock but like WBahn said, I don't know what kind of part you are using here so its kind of moot.

I don't know of any specific tutorials on these. Try looking at some data sheets for serial devices like this one for a serial memory. The timing diagrams are used to illustrate pictorially the address/data/CE sequences that are described in the text and specifications.