I have a circuit design that's highly influenced by parasitic capacitance. I need advice on how to design my PCB to minimize parasitic capacitance. I've attached the schematic. There will also be a potentiometer where M3, M4, and M7 meet to help balance this circuit.



Thanks,
Mike

 

To minimize parasitic capacitance make the critical traces as narrow as the PCB process can handle, keep a good distance from nearby traces. and have no other traces or ground plane underneath the trace.
Also keep the traces as short as possible.