How to lock this pll?

Discussion in 'General Electronics Chat' started by dumindu89, Nov 5, 2012.

  1. dumindu89

    Thread Starter Member

    Oct 28, 2010
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    Hello!
    I implemented a pll using 74s124 vco, Altera MAX II CPLD (programmble divider, referance frequency, XOR gate for the phase comparator) and a 2 nd order low pass filter. The reference frequency is 25 kHz and the free running frequency of the VCO is 30 MHz. The desired range is 22 MHz- 27 MHz and it is adjustable by the Programmable divide by N counter (25kHzxN). Although I implemented the PLL it doesn't lock.

    How I lock it? Please let me know.
     
  2. bertus

    Administrator

    Apr 5, 2008
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    Hello,

    Do you have the current schematic?

    Bertus
     
  3. ifixit

    Distinguished Member

    Nov 20, 2008
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    Goggle: phase-frequency detector
     
  4. dumindu89

    Thread Starter Member

    Oct 28, 2010
    113
    0
    Here is the schematic.

    I used Altera MAX II CPLD for the feedback loop. Programmable divided by N counter, reference frequency (divided the internal 50 MHz crystal oscillator clock signal to get the reference frequency and the XOR gate as the phase detector are implemented in the CPLD)

    [​IMG]
     
  5. kubeek

    AAC Fanatic!

    Sep 20, 2005
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    Seriously, a 741 that has trouble even with audio frequencies?
    What sort of frequency is coming out from the xor gate?
     
  6. crutschow

    Expert

    Mar 14, 2008
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    You need to show a diagram of what's implemented in the CPLD.
     
  7. bertus

    Administrator

    Apr 5, 2008
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    Hello,

    Are the phase comparator and reference frequency on the altera board?
    You can not lock a pll without a reference frequency.
    Please read the datasheet of the 4046 PLL chip.
    That might give you some insight how the phase comparators work.

    Bertus
     
  8. dumindu89

    Thread Starter Member

    Oct 28, 2010
    113
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    The reference frequency and the frequency of the feedback is not equal. Therefore me too personally think that frequency detection also should be done to lock the PLL.
    Will the PLL work with phase frequency detector without the charge pump between the PFD and LPF?

    What is the drawback with 741? Noise or what?
    What Op-amp you suggest instead of 741?

    I have no idea about that wave coming out from the XOR gate when I implemeted the PLL. However, it is a square wave with different duty cycles.
    Hi Here is the diagram.

    [​IMG]

    yep. Reference frequency is implemented by dividing the 50 MHz clock (which is generated by 50 MHz crystal) by 2000 and XOR gate is implemented as the phase detector.
     
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