Hi,
I'm new to online forum. I want to interface 74HC541(Buffer) to 74HC574(D-f/f). The thing is 100's of D-f/f parallel interface as shown in figure(Fig.1).
Input and load capacitance limits it to 10 to 15 fanout. Fanout of buffer current wants to charge input capacitance of D-f/f. So increasing D-f/f increases charge time of input capacitance.
My question is this can be overcome by giving more current to increase charge current to input capacitance by adding pull up resistor to input of D-f/f(Fig.2) or BJT emitter follower(Fig.3).
This would correct or not...

Thanks in advance...

 

Fan out of 74HC is 4000.

What you have to pay attention to is your maximum clock speed taking into account the increased capacitance and long signal runs.
Bus termination of 2kΩ pullup and 130Ω pulldown has been suggested.

http://www.nxp.com/documents/user_manual/HCT_USER_GUIDE.pdf

 

use more buffers to divide the signal into branches that feed other buffers untill you have enough fanout to drive all the FFs. If the first stage drives 15 buffers, and those each drive 15 FFs, you get 225 FFs alltogether.

(Or use an FPGA to do the logic, instead of driving hundreds of ICs, but that really depends on what the design is for...)

 

Thanks for your valuable suggestion and from your suggestion I go for buffer tree.