Hello
I build freq divider 8/12 using d flip flop, but I wonder how to make it 8/9 ?
I build my divider like:
%2/3 --> %2 ----> %2
the result is 8/12, now how can I play with gates to obtain 8/9 instead?
thanks a lot

 

Take a look at the 7497 binary rate multiplier datasheet for some ideas. It won't do exactly what you want, but you can use the circuit as a starting point.

If you don't restrict the solution space to some gates, a PLL would do it easily.

 

Use a Cd4017, set it to reset on 9.

 

I need it with cmos

 

It's simple as Dodgydave showed, if you don't need a 50% output signal duty-cycle.

 

It's simple as Dodgydave showed, if you don't need a 50% output signal duty-cycle.

Crutschow, how can i send you a pm??

 

I need it with cmos

The 4000 series is CMOS architecture.

 

Ok , but I need the circuit configuration...
Thanks

 

Crutschow, how can i send you a pm??

Sorry, I don't normally do pm's.
Can't it be answered in thread?

 

Hello
I build freq divider 8/12 using d flip flop, but I wonder how to make it 8/9 ?
I build my divider like:
%2/3 --> %2 ----> %2
the result is 8/12, now how can I play with gates to obtain 8/9 instead?
thanks a lot

Could you clarify what you mean by 8/9? I interpreted it to mean that for every 9 input clock pulses, you wanted 8 out.

Also, could you post a schematic for the circuit you referred to?

 

Hello
I build freq divider 8/12 using d flip flop, but I wonder how to make it 8/9 ?
I build my divider like:
%2/3 --> %2 ----> %2
the result is 8/12, now how can I play with gates to obtain 8/9 instead?
thanks a lot

If you've built it then you must have a schematic on hand which you could post to clear up what you mean.
For example, When you say you want an 8/9 divider, does that mean that if you put 90Hz into it you'd like to get 80Hz out?\

And what about output duty cycle and input frequency?

 

Hello
I build freq divider 8/12 using d flip flop, but I wonder how to make it 8/9 ?
I build my divider like:
%2/3 --> %2 ----> %2
the result is 8/12, now how can I play with gates to obtain 8/9 instead?
thanks a lot

8 isn't hard at all - there are old logic family databook on archive.org - there are probably application examples how to hook up standard divider stages for weird and wonderful ratios.

 

I deleted my original post. It didnt make sense (I must have been drinking). My updated response is below.

First, is the frequency you are "multiplying" by 8/9 a digital or analog signal?

If digital, read on...

Ok , but I need the circuit configuration...
Thanks

Start by multiplying your clock by 8. Or, in actuality by 2. There is a common circuit using digital logic to multiply by 2. Just apply this circuit three times to multiply by 8 (2^3=8).

Then feed the multiplied signal into a CD4017. Take output 9 and connect it to reset. Take any other output as your divide by 9 output.

This results in an 8/9 signal.

 

8GHz with CMOS?

 

I deleted my original post. It didnt make sense (I must have been drinking). My updated response is below.

First, is the frequency you are "multiplying" by 8/9 a digital or analog signal?

If digital, read on...


Start by multiplying your clock by 8. Or, in actuality by 2. There is a common circuit using digital logic to multiply by 2. Just apply this circuit three times to multiply by 8 (2^3=8).
View attachment 119160
Then feed the multiplied signal into a CD4017. Take output 9 and connect it to reset. Take any other output as your divide by 9 output.

This results in an 8/9 signal.

Interested...
I want to build 8/9 using d flip flops and I found this diagram somewhere


- what is the idea of putting these gates? just to understand to build more configurations like 15/16 or 31/32
- where I can put the output of 3-nor gate? without using Reset
Thanks

 

I made the above circuit like this ( U3 is AND gate not NOR gate)



but my results is just

 

Where is the output of your circuit? And what do each of the two traces represent?

I have trouble understanding your circuit. U1 and U2 have their clocks tied together and to nothing else. That means to me they will never change state. And you cannot predict what that state is.

I am away from any computer (on phone) otherwise I'd simulate the circuit.​

 

I'm sorry for fussy circuit.
U1, U2 is represent 2/3 divider , so I connect more 2 FF ( U5 and U6) to got divided by 4 , so whole circuit is represented 8/9 divider , this is what I understand from this diagram





But the output is wrong ( the output is from U6)

 

I found your diagram. Unfortunately, it is only a block diagram with no further explanation. Perhaps another member can explain it.

My questions remain unanswered, so at this time I can't help further. I like the idea of the diagram because it appears simpler than the brute force approach I have in mind (multiply by 2 three times, divide by 3 twice).

 

Is this for an RF pre scaler ?

as used in frequenciey multipliers in radios ?

something like this ?

http://www.wseas.us/e-library/conferences/2007corfu/papers/540-119.pdf