# How to create this output?

Discussion in 'Digital Circuit Design' started by rocafellachild, Sep 2, 2016.

1. ### rocafellachild Thread Starter New Member

Sep 2, 2016
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0
Hello

I have a basic knowledge of gates and flipflops and have come across this problem.
I have Input 1 and Input 2 going into a circuit made up of simple logic parts(gates, transistors, flip flops) but no microcontrollers. I have one output. (see picture)

I want the output to be high when (Input1=1 and the rising edge of Input2). I want the output to be low when (Input2=0 and the falling edge of Input1).

I've been trying to figure out a combination of logic to see if I can get this output but I think I'm stuck. Can someone suggest an approach on how to solve a problem like this?

2. ### AlbertHall Well-Known Member

Jun 4, 2014
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For the particular inputs you show this circuit will do the job. Is IN2 being high guaranteed to be only while IN1 is high?

3. ### dannyf Well-Known Member

Sep 13, 2015
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IN2 sets the output and IN1 resets the output.

4. ### rocafellachild Thread Starter New Member

Sep 2, 2016
2
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I don't think a simple S-R flip flop will work because:
1. I have a case where both the S and R are high at the same time
2. I need the reset to occur on the falling edge.

5. ### k7elp60 Senior Member

Nov 4, 2008
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Use two 2 input nand gates

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6. ### AnalogKid Distinguished Member

Aug 1, 2013
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For a NOR gate S-R flipflop, a positive level changes state. Use an extra NOR gate as an inverter for IN1 before the ff. Take the output from the ff with inverted IN1 as its input.

ak

7. ### ScottWang Moderator

Aug 23, 2012
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You didn't mention the frequency of inputs signals and the working voltage, the output load V/I?

8. ### AnalogKid Distinguished Member

Aug 1, 2013
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Scott, there is no need for C2 or R5. Q1 collector can tie directly to the reset input. According to post #1, it is ok for the circuit to be sitting in Reset between events. Also no need for R2 because the input is driven in both directions.

ak

9. ### ScottWang Moderator

Aug 23, 2012
4,935
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Thanks Ak.
I have had thought about that, but I'm not sure, because I just want to avoid the S/R have any chance to conflict, and I just found that I missed the waveform for /Vin1, when I redraw the waveform then it's quite clear, S/R have no chance to conflict.

I have had also thought about that, but I will keep it until the condition more clear.

10. ### AlbertHall Well-Known Member

Jun 4, 2014
2,290
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This gives the wrong output for the given waveforms when IN1 has gone low but IN2 is still high. The output for will be a copy of IN1.

11. ### AnalogKid Distinguished Member

Aug 1, 2013
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According to post #1, that condition cannot occur.

ak

12. ### AnalogKid Distinguished Member

Aug 1, 2013
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What you end up with is an inverter in front of a positive-logic S-R ff, just like post #6.

ak

13. ### AlbertHall Well-Known Member

Jun 4, 2014
2,290
451
Correction:
I wrote IN1 and IN2 the wrong way round - but the two nand gate circuit still doesn't work.
This gives the wrong output for the given waveforms when IN2 has gone low but IN1 is still high. The output for will be a copy of IN2.

14. ### AnalogKid Distinguished Member

Aug 1, 2013
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Yes, post #5 clearly is wrong. There is no linear gating solution.

ak

15. ### hp1729 Well-Known Member

Nov 23, 2015
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View attachment 111494

16. ### eetech00 Active Member

Jun 8, 2013
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Hi

I think this will work.
Voltages used in the simulation are 1,0v logic levels but should work for other levels.

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17. ### AlbertHall Well-Known Member

Jun 4, 2014
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451
But it is way more complicated than is necessary. The version in post #2 works, except that I got IN1 and IN2 swapped