Dear All,

I have below doubt -

1. How many maximum no of I2C slave(Lets say EEPROM/other) can be driven by I2C master(Lets say microcontroller). What all are the physical limiting factors means how do find this .

2. How many maximum no of SPI slave(Lets say EEPROM/other) can be driven by SPI master(Lets say microcontroller). What all are the physical limiting factors means how do find this .

 

The theoretical number is limited by the bits allowed in the address. Thus, an 8-bit register allows a 7-bit address, or 127 slaves.
http://electronics.stackexchange.com/questions/181953/how-many-i2c-slaves-can-a-i2c-master-support

John

 

Another limitation, that is harder to quantify, is the length of the clock and data lines. For both I2C and SPI the signal lines are single ended. These interfaces were designed to be used on a single board, or perhaps on boards within a system of limited size(2 ft^3). Neither interface is designed for connecting network nodes on a factory floor. As the length of the clock and data lines are increased you will experience an increase in capacitance and an increase in resistance. Thee increase in capacitance will have the effect of slowing down the edges, while the increase in resistance will attenuate the signals making them more susceptible to noise and distortion.

My rule of thumb is to limit I2C and SPI path lengths to 18 inches with a handful of nodes, like maybe 4-6 nodes. To go further or to add more nodes would require some investigation.

 

Another limitation, that is harder to quantify, is the length of the clock and data lines. For both I2C and SPI the signal lines are single ended. These interfaces were designed to be used on a single board, or perhaps on boards within a system of limited size(2 ft^3). Neither interface is designed for connecting network nodes on a factory floor. As the length of the clock and data lines are increased you will experience an increase in capacitance and an increase in resistance. Thee increase in capacitance will have the effect of slowing down the edges, while the increase in resistance will attenuate the signals making them more susceptible to noise and distortion.

My rule of thumb is to limit I2C and SPI path lengths to 18 inches with a handful of nodes, like maybe 4-6 nodes. To go further or to add more nodes would require some investigation.

There are i2c extender ic. So I would go with the jpanhalt answer to this homework.

 

The receiving ICs will have some capacitance. The driving MCU must have enough strength to drive them all. In I2C case, the slaves must be able to drive the line too. So, there is a limit. In practice, I've never hit it.

SPI is different. You can send to many. Unless you send the same, you need a separate SS line for every slave. For receiving, you need your slaves to cooperate and to tri-state their outputs when their SS is not active. Some of them do this, some don't.

 

You can also Daisy-Chain compatible devices with SPI.
https://www.maximintegrated.com/en/app-notes/index.mvp/id/3947
http://www.ti.com.cn/cn/lit/an/snaa070a/snaa070a.pdf

 

There are i2c extender ic. So I would go with the jpanhalt answer to this homework.

I doubt that anyone would construct such a network, but just for the record there is a 10 bit address version so I guess that makes 1024 nodes.

 

You can also Daisy-Chain compatible devices with SPI.
https://www.maximintegrated.com/en/app-notes/index.mvp/id/3947
http://www.ti.com.cn/cn/lit/an/snaa070a/snaa070a.pdf

nsa, I did not read the links, so don't be too rough on me. From my small experience, only clock and data lines can be daisy chained when using spi. The chip select/device select lines are still need to be run individually, one for each spi chip/device.

The basic answer to OP question regarding spi is: take number of pins, subtract two pins, the remainder is the number of devices you can have when using spi. The two subtracted pins are clock signal line and data signal line, they are shared by all the spi devices.

 

nsa, I did not read the links, so don't be too rough on me. From my small experience, only clock and data lines can be daisy chained when using spi. The chip select/device select lines are still need to be run individually, one for each spi chip/device.

SPI is a shift register protocol that can be cascaded (serial out from one device to the serial in on the next device) to increase the number of bits stored in the chain with the correct logic. For devices like a shift-register compatible serial DAC cascade with a register load pin it's possible to clock data to all device receive registers in the chain then latch the data with that load pin into the devices for analog outputs.

http://jumptuck.com/2011/11/03/how-to-drive-595-shift-registers-with-avr-hardware-spi/

 

SPI is a shift register protocol that can be cascaded (serial out from one device to the serial in on the next device) to increase the number of bits stored in the chain with the correct logic. For devices like a shift-register compatible serial DAC cascade with a register load pin it's possible to clock data to all device receive registers in the chain then latch the data with that load pin into the devices for analog outputs.

http://jumptuck.com/2011/11/03/how-to-drive-595-shift-registers-with-avr-hardware-spi/

Thank you. I will see what I can learn.