How does the FET feedback works

Thread Starter

vustudent

Joined Mar 11, 2009
38
Here is a four resistor biasing circuit, I know that the RS resistor would provide negative feedback. However, I have problem in explaining how the whole feedback process works, please help.
 

Ron H

Joined Apr 14, 2005
7,063
You should have ≈3V on the source, not 0V.
If Ids tries to increase, Vgs will decrease (do you understand why?), which will tend to reduce Ids. Voila! Negative feedback.
 

Audioguru

Joined Dec 20, 2007
11,248
Your schematic looks awful.
It was saved as a fuzzy JPG file type instead of as a very clear GIF or PNG file type.
It is covered with Measles dots.

Why does Multisim DO DAT?
 

Thread Starter

vustudent

Joined Mar 11, 2009
38
You should have ≈3V on the source, not 0V.
If Ids tries to increase, Vgs will decrease (do you understand why?), which will tend to reduce Ids. Voila! Negative feedback.
I understand that
Vgs= Vth-Rs(Id)

when Vth increases Vgs will increase, which Id will increase and resulting a decrease in Vgs. However, how do you explain the correlation between such a negative feedback towards having smaller output gain at Vout?
 

Thread Starter

vustudent

Joined Mar 11, 2009
38
Your schematic looks awful.
It was saved as a fuzzy JPG file type instead of as a very clear GIF or PNG file type.
It is covered with Measles dots.

Why does Multisim DO DAT?

Sorry my computer knowledge is awful, I just built my circuit in pspice and bracket, copy to clipboard and paste somewhere as a pic.
 

KL7AJ

Joined Nov 4, 2008
2,229
Sorry my computer knowledge is awful, I just built my circuit in pspice and bracket, copy to clipboard and paste somewhere as a pic.
Your schematic looks fine here. Of course, I always use ICAP4, so I'm used to measle dots. :)

Yes, this is classic CURRENT feedback, (acutally very commonly used in old vacuum tube class A power amplifiers). As current through the source increases, the voltage at the top end of the source resistor increases. This puts it at a higher voltage relative to the gate...in effect this LOWERS the gate voltage. This, in turn, tends to decrease the source current.
The RC network from the drain to ground makes the overall gain frequency sensitive. This rolls off the gain of the device at higher frequencies, as it forms a voltage divider, lowering the source voltage progressively as the frequency is increased. This is quite independent of the feedback loop.

Hope this helps.


Eric
 
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