In a parallel register memory using, say 4 D Flip-flops, it is said that the output will essentially be stored. So if I had D3=0, D2=0, D1=1, D0=1, the parrellel register will remember 0011.

But will this storage of 0011 be stored only when the clock signal is low? So when I change the input during the clock's low signal, the output will not be affected. But when clock's signal is high again, the output will be changed, erasing the previous output, right?

Then in this case, what is it remembering? Wouldn't it be just similar to something like a decoder or multiplexer, where the output just changes according to the input? Unless the output only gets reset by its active-low reset and doesn't get changed by its input, it doesn't sound like "storing" anything to me.

Also, if the D Flip-flop has an active-low reset, it has no use either, isnt it? I could change my input to 0000 and then on the clock's next high signal, the output will be reset to 0000 too. What's the point of the active-low reset?

thanks.

 

Take a look here at a typical shift register. As you can see, it contains D Flip Flops, which can actively store the output data. Those specific FFs change on the negative front of the clock pulse. Any input inserted on the circuit will be recognised and forwarded to the output only on the negative front of the pulse.

Check this image:
http://forum.allaboutcircuits.com/attachment.php?attachmentid=23812&d=1287856885
found in this similar thread:
http://forum.allaboutcircuits.com/showthread.php?t=44573&highlight=shift+register

A MUX is used of course, to select the input, but in case 00, the signal is just fed back from the D-FF output. The D-FF is necessary to prevent any race conditions between the various gates of the circuit.

The reset signal is necessary when you don't have direct control over the inputs of the latch.