How do you make a 2-bit Synchronous down counter using D type flip flop?

Discussion in 'Homework Help' started by Dntk1, Dec 31, 2012.

  1. Dntk1

    Thread Starter New Member

    Dec 31, 2012
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    Can anyone help me design the circuit its self and also the state table The sequence should be 3 2 1 0
     
  2. tshuck

    Well-Known Member

    Oct 18, 2012
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    This sounds oddly like a homework problem....

    So I'll ask you, what have you done to solve this?
     
  3. Dntk1

    Thread Starter New Member

    Dec 31, 2012
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    Ive been able to determine the present and the next states where the present states are

    00
    01
    10
    11

    Where the next states will be

    11
    00
    01
    10

    for the sequence 3210
     
  4. bertus

    Administrator

    Apr 5, 2008
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  5. Dntk1

    Thread Starter New Member

    Dec 31, 2012
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    Can you please help me?
     
  6. bertus

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  7. MrChips

    Moderator

    Oct 2, 2009
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    You can do this with Karnaugh mapping or you can do this intuitively.
    Ask yourself, under what condition of the D-input does the D-type flip-flop go high?
     
  8. WBahn

    Moderator

    Mar 31, 2012
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    So put this information into a single table.

    Q1 Q0 Q1n Q0n
    0 0 1 1 (typo fixed - Q0n was 0 before)
    0 1 0 0
    1 0 0 1
    1 1 1 0


    Now extend the table with excitation values (for each FF, call these D1 and D0). Hint, for a DFF, thisi is trivial).

    Then determine the logic equation (or gates) that will take you from the current state outputs to the next state inputs for each DFF.
     
    Last edited: Jan 1, 2013
  9. MrChips

    Moderator

    Oct 2, 2009
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    Don't let WBahn confuse you. He made a typo on line 1.
     
  10. WBahn

    Moderator

    Mar 31, 2012
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    Thanks for catching that, MrChips.
     
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