How do the access transistors in an SRAM cell work?

Discussion in 'General Electronics Chat' started by NotAnt, Mar 31, 2015.

  1. NotAnt

    Thread Starter New Member

    Mar 31, 2015
    For example, in the circuit above, where is the source of M5 and M6 connected to? because no matter where it is connected I don't understand how they could operate. If the source is connected to the inverters:
    how can they be turned on by simply asserting WL? wouldn't the transistors turn on or off based on the gate-source voltage? I don't understand how, for example, it would be possible to turn on M6 when there is a 1 stored in Q. In that case asserting WL would only bring the gate-source voltage to 0, how can that be enough to turn it on?

    The usual explanation of the operation of the SRAM cell relies on both access transistors being turned on. You can find an example here ( So I don't understand how the access transistors could be both turned on if the source was on the side of the bit lines (because you are bringing BOTH bit lines to HIGH during a read operation).

    Even if the source was on the side of the inverters I don't understand how they work, because then only one access transistor would be turned on during a write operation, the same that would be turned on during a read operation (because now the only thing that matters to turn on the access transistors is Q and -Q: remember that source is on the side of the inverters). If both reading and writing turned on the same transistors provided that the contents of the cell are the same, then what's the difference between reading and writing? I don't think it's just the sense amplifier. I would like for someone to clear these doubts.
  2. dl324

    Distinguished Member

    Mar 30, 2015
    Hi NotAnt,

    M5 and M6 are switches that are controlled by WL. A logic 1 on WL turns both on. What the storage element does depends on whether a read or write operation is being performed.

  3. MikeML

    AAC Fanatic!

    Oct 2, 2009
    Typically, to read, you pre-charge the bit lines BL and BLbar to about Vdd/2, and then assert the WL line. The cell drives the bit lines such that one gets more positive while the other goes the other way. A sense amplifier tied differentially to the bit lines reads the voltage difference after some time to see if a one or zero is stored in the cell.

    To write to the cell, the bit lines are driven from a low-impedance driver so when the WL line is asserted, the cell is actually flipped by the current injected into the cell via M5 and M6.