hi, i have this linear amplifier project http://tzitzikas.webs.com/irf640-1.JPG with 2 irf640 mosfets.
My problem is, when i adjust the both mosfets drain's current at 400mA (current without input signal), after some minutes when the heatshink is warm (with input signal), the current becomes very high and one of the 2 fet goes off, and i must replace it. Do you have any idea-schematic (with thermistor or diode) to control this current and to keep it stable at 400mA?

 

Sounds like your heat sink is not large enough to dissipate the heat.

As MOSFETs heat up, their Rds(on) increases. That should decrease the current flow. However, if you don't have sufficient heat sinking, they are going to burn up.

Are you using 12v for V1? If so, with 400mA current, you need to dissipate 4.8W of power per MOSFET with the amplifier idling.

From the junction to the heatsink (assuming a perfect union using heat sink compound and snugly fitted) you have a thermal resistance of 1.5°C/Watt, so you have a 7.2°C rise from ambient air temp even if you have a perfect heat sink.

Without a heat sink, thermal resistance junction to ambient is 62°C/Watt, so your idle requirement would place the MOSFET junction at 297.6°C above the ambient air temperature (probably 22°C-25°C indoors) - you'd fry it mighty quickly.

 

Not bad if your making a cigarette lighter, but s large enough heat sink and thermal compound for good thermal transfer/conduction.

The first step is to use MOSFETS that are closely matched to the requirements of the design. That will keep the amount of heat needed dissipating to a minimum.

Once that point is reached, a heat sink in open air or a heat sink and fan can be added to the design.

 

here you can see some photos from my linear. sometimes i am using 4 mosfet (2+2)
http://tzitzikas.webs.com/linear2xirf640-1.jpg
http://tzitzikas.webs.com/linear2xirf640-2.jpg
http://tzitzikas.webs.com/linear2xirf640-3.jpg
i don't know if the problem is the heatshink, because i am using a fan for cooler and the heatshink is cold.
do you have any idea (thermistor or diode) to modificate the circuit to keep stable the drain's current?

 

It looks like the 4.7 ohm series gate resistors are too far away from the gate pins of the Mosfets so the Mosfets oscillate at a VHF frequency and get extremely hot.

A heatsink has a large surface area because it has fins. The fins are close to the heat source. The mounting surface is smooth and flat. The material is aluminum that is anodized black to radiate heat well. Aluminum conducts heat well.
You show pieces of flat metal which are not good heatsinks.

 

Thank you for your answers
The designer have propose to me, because i have this problem, to increase the gate's series resistors from 4.7ohm to 10ohm and to add at the sources series resistors 0.1ohm. When i did these replacements, the linear was more stable, i don't have problem with the mosfets but the output power was lower. So i kept the 0.1ohm resistances at gates, but i put again 4.7ohm resistors at gates. After this replacement i had problem with the mosfets again.
What value of resistors do you propose to add at gates and at sources? 0.1ohm at sources do you think is so small resistance? 1 ohm resistors at gates do you believe that will decrease more the output power?

 

One thing I don't see is a way to keep the gates from exceeding +/-20Vgs. If that happens, the MOSFET will be destroyed. You should probably add clamping Zeners to prevent such damage.

Back-to-back 15v Zeners from gate to source should take care of that.

 

One thing I don't see is a way to keep the gates from exceeding +/-20Vgs. If that happens, the MOSFET will be destroyed. You should probably add clamping Zeners to prevent such damage.

Back-to-back 15v Zeners from gate to source should take care of that.

hi. lm7805 regulator don't protect? the maximum Vgs is 5volt with the regulator 7805.
i don't understand why i must use 15v zener diodes. And if i must add them, i must connect the anode of zener to source and the cathode to the gate? One zener for each mosfet?
(see this schematic: http://tzitzikas.webs.com/linear2w-zener.JPG )
this zener don't create parasitic capacitance between gate-source?

 

You would need two Zeners back-to-back from the gate to ground for each MOSFET, like this:

G ---|>|---|<|--- S

You are only showing a single Zener per gate.

No, the 7805 won't protect it.

Transformer secondaries can have a phenomenon known as "flux walk". I don't know if that is occurring in your amp, but adding a pair of Zeners on each gate will protect the MOSFET if flux walking occurs.

There may be some parasitic capacitance in the Zeners. It will be very small compared to the gate charge.

 

My two cents...

1. The layout looks poor for 2MHz operation.
2. If possible; use linear-mode transistors, not switch-mode MOSFETs.
3. It is not easy to keep a stable bias with temperature unless you use some kind of positive feedback. A 1Ω source resistor to ground will be a good start, and you can measure the current in each driver to verify the bias is equal.
4. The gate input bias is not perfectly balanced. It should be. Connect another 10K resistor from C9 to R6. Even better would be for the gate drive transformer secondary to have a center tap for biasing input.
5. At 2MHz it doesn't take much capacitive imbalance either... ensure your layout/wiring is symetrical.
6. C4 is 3.3n... that's 96Ω to 24Ω at the 500KHz to 2MHz range... seems a little too low impedance.
7. The output transformer seems to be 500mH... way too high for your frequency of operation.
8. With only 4 turns on #43 ferrite, what is the inductance?
9. What is the design output impedance?

Regards,
Ifixit

 

First of all, thank you very much for your answers.

My two cents...

1. C4 is 3.3n... that's 96Ω to 24Ω at the 500KHz to 2MHz range... seems a little too low impedance.
2. The output transformer seems to be 500mH... way too high for your frequency of operation.
3. With only 4 turns on #43 ferrite, what is the inductance?
4. What is the design output impedance?

Regards,
Ifixit

About C4=3.3n. The linear at 1200khz gives at output 4w r.f power with 18vdc voltage and at 1450khz gives only 2,5w.
Do you believe that the c4=3.3n is improper value? What value do you suggest for this capacitor?
I would like to have 4w at 1450khz. ( when i increase the carrier's frequency above 1450khz, the output power is been dicreased
more. At 1700khz the output power is 1,5w only).
Do you have to suggest any other modification in circuit to have the same power at all mw frequencies?
A modification about transformers or c4 capacitor or other capacitors?
the output is 50ohm. (but i could not measure it)

You would need two Zeners back-to-back from the gate to ground for each MOSFET, like this:

G ---|>|---|<|--- S

You are only showing a single Zener per gate.

SgtWookie like this schematic? : http://tzitzikas.webs.com/linear2w-zener2.JPG

My two cents...

1. The gate input bias is not perfectly balanced. It should be. Connect another 10K resistor from C9 to R6. Even better would be for the gate drive transformer secondary to have a center tap for biasing input.

Regards,
Ifixit

About the 10k resistor. See the schematic http://tzitzikas.webs.com/linear2w-10k.JPG .You propose ta add a second 10k resistor to the other gate from C9 to R6.
I think it could be better to add 2 resistors 20k 1 at each mosfet, to have a value of 10k again in paraller.
What do you think? If i add a second resistor 10k, maybe i will have problem because the whole resistor value (in paraller)
will be 5k.

 

Hi tzitzikas,

I ran some simulations and have some further suggestions...

1. Change C4 to 220pF to roll-off the frequency response after 2MHz, or leave it out for now.
2. Move C2 to be in parallel with R1 47Ω. This will increase the gain of the first stage. There should be no cap across R4 because it will limit the drive signal.
3. Remove C5 10n because it also limits the signal.
4. Operate the driver MOSFETs in Class B mode to reduce distortion and power waste. Bias them around 40mA instead.
5. Add 1Ω resistors to the sources.
6. The IRF640 has a gate capacitance of 1600pF, which is an impedance of 50Ω at 2MHz and 200Ω at 500KHz. To keep the response flat they should be driven with a 5Ω source impedance. Since R4 is 33Ω, that is not going to happen.
7. The T2 pre-driver stage will be very in-efficient driving into 5Ω. An M1 with a center tapped output would be better.
8. The output stage seems to work good, its the driver stage that needs some changes. I'm just not sure what your options are.
9. How flat does the output response have to be?

Try the above changes and let us know how if the over heat is cured and the response is flatter.

Regards,
Ifixit

 

SgtWookie like this schematic? :

Yes, that's what I meant.

 

Hi tzitzikas,

I ran some simulations and have some further suggestions...

1. Change C4 to 220pF to roll-off the frequency response after 2MHz, or leave it out for now.
2. Move C2 to be in parallel with R1 47Ω. This will increase the gain of the first stage. There should be no cap across R4 because it will limit the drive signal.
3. Remove C5 10n because it also limits the signal.
4. Operate the driver MOSFETs in Class B mode to reduce distortion and power waste. Bias them around 40mA instead.
5. Add 1Ω resistors to the sources.
6. The IRF640 has a gate capacitance of 1600pF, which is an impedance of 50Ω at 2MHz and 200Ω at 500KHz. To keep the response flat they should be driven with a 5Ω source impedance. Since R4 is 33Ω, that is not going to happen.
7. The T2 pre-driver stage will be very in-efficient driving into 5Ω. An M1 with a center tapped output would be better.
8. The output stage seems to work good, its the driver stage that needs some changes. I'm just not sure what your options are.
9. How flat does the output response have to be?

Try the above changes and let us know how if the over heat is cured and the response is flatter.

Regards,
Ifixit

thank you for your answers.
The output must be sine wave without any distortion.
i would like the linear to give the maximum output power at range 1300-1600khz.
About 4: <<4. Operate the driver MOSFETs in Class B mode to reduce distortion and power waste. Bias them around 40mA instead.>> What do you mean about <<Bias them around 40mA instead.>>?? Ho i can operate the driver MOSFETs in Class B mode??
But i think the linear must operate at Class-A to achieve the best audio quality in modulation
About (R4 =33Ω) what value do you propose?
<<Change C4 to 220pF to roll-off the frequency response after 2MHz, or leave it out for now.>> <-- What do you mean with the phrase "to roll-off the frequency". I don't understand it. My English are not very good.

About your suggestion "Move C2 to be in parallel with R1 47Ω. " . I tried to simulate this change with Tina Industrial, the output signal of BC546 had been increased But the output sine wave (of BC546) had distortion.

 

<<Change C4 to 220pF to roll-off the frequency response after 2MHz, or leave it out for now.>> <-- What do you mean with the phrase "to roll-off the frequency". I don't understand it. My English are not very good.

That means signals at high frequencies will be attenuated (reduced, decreased, absorbed, made smaller) - think of it as a low-pass filter (lower frequency signals will pass through, but higher frequency signals will be attenuated.)

 

1. Class B should not effect signal quality except at the cross-over because it is a push-pull arrangement... when one side is off, the other is on. Just keep a small bias to minimize the cross-over distortion. In any case, it very easy to turn up the bias later if you need to. A test will tell.
2. The output transformer has a 1:2 ratio in order to get the 20V peak signal out that is required for 4 Watts RMS across 50Ω.
3. This means the input needs to swing 10V ± of the 12V rail, which the class B will do.
4. A 12V rail is barely enough for your requirements.
5. Your MOSFET have 1600pf gate capacitance... way too much. Can you use IRF510s instead?
6. Each stage of a linear amp must be kept resistive in order to get a flat response over the frequency range of interest. To do this, you must drive the MOSFETs from a 5Ω source in order to over come the effects of the high gate cap. Your 10K bias method does not work for this reason. Use a center-tapped transformer, and bias the center-tap and de-couple with 0.1uF.
7. The T1, T2 stage cannot drive 5Ω well enough to meet your requirements, so the M1 transformer should have a higher turns ratio such as 3:1. T2 would then only have to drive into 90Ω. I am assuming the output side is center-tapped at 5Ω on each half for the gate drive.
8. You need to buy a copy of the; ARRL Handbook for Radio Communications. (Use Google)
9. With a specification of only 100mV RMS in, you will need a power gain of 43dB. You will never get that with this circuit. Hopefully, you can drive the input with at least 1 or 2 Volts.
10. My suggestion to put C2 with R1 is no good so don't do it. It changes the frequency response much more than I expected. The gain stage will have to stay as is and you will need more input signal.

I have tried to explain my methods so you can figure things out for yourself and not have to blindly trust someguy on the internet. Post questions and I/we will answer them.

Good Luck trying some of the changes,
Ifixit.

 

1. Class B should not effect signal quality except at the cross-over because it is a push-pull arrangement... when one side is off, the other is on. Just keep a small bias to minimize the cross-over distortion. In any case, it very easy to turn up the bias later if you need to. A test will tell.
2. The output transformer has a 1:2 ratio in order to get the 20V peak signal out that is required for 4 Watts RMS across 50Ω.
3. This means the input needs to swing 10V ± of the 12V rail, which the class B will do.
4. A 12V rail is barely enough for your requirements.
5. Your MOSFET have 1600pf gate capacitance... way too much. Can you use IRF510s instead?
6. Each stage of a linear amp must be kept resistive in order to get a flat response over the frequency range of interest. To do this, you must drive the MOSFETs from a 5Ω source in order to over come the effects of the high gate cap. Your 10K bias method does not work for this reason. Use a center-tapped transformer, and bias the center-tap and de-couple with 0.1uF.
7. The T1, T2 stage cannot drive 5Ω well enough to meet your requirements, so the M1 transformer should have a higher turns ratio such as 3:1. T2 would then only have to drive into 90Ω. I am assuming the output side is center-tapped at 5Ω on each half for the gate drive.
8. You need to buy a copy of the; ARRL Handbook for Radio Communications. (Use Google)
9. With a specification of only 100mV RMS in, you will need a power gain of 43dB. You will never get that with this circuit. Hopefully, you can drive the input with at least 1 or 2 Volts.
10. My suggestion to put C2 with R1 is no good so don't do it. It changes the frequency response much more than I expected. The gain stage will have to stay as is and you will need more input signal.

I have tried to explain my methods so you can figure things out for yourself and not have to blindly trust someguy on the internet. Post questions and I/we will answer them.

Good Luck trying some of the changes,
Ifixit.

i am thinking to change the M1 transformer ratio, to give more signal to the gates. Do you mean 1:3? I would like to tell me, how many turns must have the primary coil
of M1 (the coil after BD139) and how many turns must have the secondary coil of M1 (the coil which is connected with tha gates resistors).?
I am afraid if this change destroy the output signal and add distortion.
For this transformer i am using an FT50-43 ferrite.
about the the output side of M1 transformer (you said "Use a center-tapped transformer, and bias the center-tap and de-couple with 0.1uF."), do you mean this connection? : http://tzitzikas.webs.com/irf640-mod.jpg
the ferrite is FT50-43 ( http://www.rpelectronics.com/Data/FER-CORES.JPG )
how many turns must have the primary coil of M1 and how many turns must have the one of 2 parts of secondary coil of M1? (you mean to keep 3 turns fro primary coil and the secondary for 1:3 ratio to have 9 turns (4.5+4.5)? 4.5 turns for each of 2 parts)??i think its difficult to achieve 4.5+4.5 turns with this ferrite. Maybe i must use another ferrite like BN-43-3312 (this ferrite i am using in output stage [M2 transformer] see this link http://s3.amazonaws.com/bhs_amidon/086mi2cpkjjswcn7_o.jpg .). what do you think?

Also do you propose to keep c2 and c5 capacitors in the circuit or to remove them??


see these photos:
http://tzitzikas.webs.com/linear2xirf640-1.jpg
http://tzitzikas.webs.com/linear2xirf640-2.jpg
http://tzitzikas.webs.com/linear2xirf640-3.jpg

thank you very much for your assistance.

 

Hi,

Yes, that is the bias method to use. C2, C5, & C4 are not required, but that the least of your problems. The transformers don't seem to have the inductance they need.

I can’t re-design your whole circuit for you, but I can give you examples of how to do it yourself with the resources and abilities you have available where you are.

Where are you anyway? I’m GMT -4.

Let’s review your requirements and then consider your design and changes required. You need to review each of these items and answer any questions. You can change any spec, or add any that I forgot.


Specifications for a RF linear power amplifier:

• Frequency range (Fr) from 500 KHz to 2 MHz.
• Flat frequency response over (1) ±1dB.
• Powered from 12 Volts DC. Can we go higher or lower?
• Input impedance 50 Ω. Is that correct?
• Maximum input signal level: 100mV RMS (200uW). Correct?
• Output power is 2 Watts into 50 Ω as per schematic. Did you mention you wanted 4 Watts? Which do we design to?
• Based on (6), the amplifier power gain required is 40dB for 2W RMS output.
• Signal-to-noise ratio?
• Signal distortion?
• Signal phase shift over Fr.

To save time let’s consider the output transformer (M2) now. 4 turns on the FT50-43 core equals 3.5uH, which at 2MHz is 50 Ω (reactive). Since your load is 50 Ω resistive, you will not get a very flat response because the transformer Z will change with frequency. The proper procedure is to get the transformer effects so low they can be ignored.

Transformer Design…

• Output V = √ (2W x 50 Ω) = 10V RMS, or 14.14 V peak. Since we can’t get this with a 12V supply, a 1:2 ratio transformer will be required.
• Secondary inductive reactance needs to be at least 10 times greater than the output Z at the lowest frequency (500 KHz). 50 Ω X 10 = 500 Ω. Therefore min inductance required is: 159uH. Let’s try to round that up to 200uH. XL at 2MHz would then be 2513 Ω, and 626 Ω at 2MHz. This is likely far enough away from 50 Ω that we can ignore the effects when the frequency changes.
• You want to use an FT50-43 core, which has a mu of ~950, & an AL value of 440. Therefore # of turns req’d is: 1000 x √ (0.2mH / 440) = 21 Turns.
• Since the primary needs the same amount, that’s 42 turns. This requires 40cm of #24 coated wire for each side. Center-tap the primary at 10 turns per side. If you think you need more room for wire you can use the FT114-43 core.
• With a 50 Ω output Z, the primary Z will be: 50 Ω / N2 = 12.5 Ω. This will be doubled and center-tapped because we are using a push-pull driver arrangement.
• The MOSFETs will need to drive peak values of approximately 5 Volts per side into 12.5 Ω. That’s 0.4A, 2.4W peak in each driver. Use the IRF510, or equivalent, because it has a lower gate capacitance of only 150pF.
• The Xc of 150pF at 2MHz is 530 Ω. We can drive this from a 33 Ω source Z and still be flat within 1dB because the circuit looks mostly resistive over the frequency range. Is that okay?

MOSFET Driver Transformer Design…

• M1’s 3 turn secondary give us only 4uH. No good.
• Let’s use the M1 design and make the secondary the center-tapped (CT) output to the gates. Terminate each gate with a 33 Ω resistor to the CT.
• The 33 Ω reflects to the primary as 33 x 4 = 132 Ω. This will be easier on the driver, BD139. We need 1.3 V to the gate, so 2.6 V peak, or 5.2 Vp-p will be needed from the class A BD139 driver.
• You can test these changes by driving the M1 primary directly from your signal generator. It should look very flat and stable.

The current transistor circuit seems to be very poor and needs re-design.

See you tomorrow.
Ifixit

 

Yes, that is the bias method to use. C2, C5, & C4 are not required, but that the least of your problems. The transformers don't seem to have the inductance

they need.

I can’t re-design your whole circuit for you, but I can give you examples of how to do it yourself with the resources and abilities you have available where

you are.

Where are you anyway? I’m GMT -4. (i am from Greece)

Let’s review your requirements and then consider your design and changes required. You need to review each of these items and answer any questions. You can

change any spec, or add any that I forgot.


Specifications for a RF linear power amplifier:
Frequency range (Fr) from 500 KHz to 2 MHz. (yes, but the frequencies that i consider more are 1200-1600khz)
Flat frequency response over (1) ±1dB. (i don't understand this)
Powered from 12 Volts DC. Can we go higher or lower? (my power supply is with lm338k and the available voltage is 12-28vdc / 5A)
Input impedance 50 Ω. Is that correct? (yes)
Maximum input signal level: 100mV RMS (200uW). Correct? (i don't know exactly but see the circuits which i use to drive it. It is
an oscillator with TDA1072 which i control by using PLL, and after is a modulator with MC1496. here is the schematics:
oscillator:
http://tzitzikas.webs.com/oscillator-1.JPG
modulator:
http://tzitzikas.webs.com/modulator-1.jpg ) [ i have a problem with the modulation signal. It is not in the center of the frequency of carrier but a little

above]Output power is 2 Watts into 50 Ω as per schematic. Did you mention you wanted 4 Watts? Which do we design to? (the designer claims that
this amplifier gives 2w rms at 12volt, 6w rms with 20volt and 10w rms with 28volt voltage with 2 mosfets. I can put +2 mosfets to have 4 (2+2) for more

power). I want to have 9-10watt maximum r.f power.)Based on (6), the amplifier power gain required is 40dB for 2W RMS output.
Signal-to-noise ratio?
Signal distortion? (i want the amplifier to have not any distortion, because the distortion causes negative to the audio quality of modulation)Signal phase shift over Fr.
To save time let’s consider the output transformer (M2) now. 4 turns on the FT50-43 core equals 3.5uH, which at 2MHz is 50 Ω (reactive). Since your load is

50 Ω resistive, you will not get a very flat response because the transformer Z will change with frequency. The proper procedure is to get the transformer

effects so low they can be ignored. (output transformer have been built with BN-43-3312 ferrite not with FT50-43. [primary is 1+1 turns and secondary

4turns]. See the photos links to my previous posts).

Transformer Design…

Output V = ? (2W x 50 Ω) = 10V RMS, or 14.14 V peak. Since we can’t get this with a 12V supply, a 1:2 ratio transformer will be required.
Secondary inductive reactance needs to be at least 10 times greater than the output Z at the lowest frequency (500 KHz). 50 Ω X 10 = 500 Ω. Therefore min

inductance required is: 159uH. Let’s try to round that up to 200uH. XL at 2MHz would then be 2513 Ω, and 626 Ω at 2MHz. This is likely far enough away from

50 Ω that we can ignore the effects when the frequency changes.
You want to use an FT50-43 core, which has a mu of ~950, & an AL value of 440. Therefore # of turns req’d is: 1000 x ? (0.2mH / 440) = 21 Turns.
Since the primary needs the same amount, that’s 42 turns. This requires 40cm of #24 coated wire for each side. Center-tap the primary at 10 turns per side.

If you think you need more room for wire you can use the FT114-43 core.
With a 50 Ω output Z, the primary Z will be: 50 Ω / N2 = 12.5 Ω. This will be doubled and center-tapped because we are using a push-pull driver arrangement.
The MOSFETs will need to drive peak values of approximately 5 Volts per side into 12.5 Ω. That’s 0.4A, 2.4W peak in each driver. Use the IRF510, or

equivalent, because it has a lower gate capacitance of only 150pF.
The Xc of 150pF at 2MHz is 530 Ω. We can drive this from a 33 Ω source Z and still be flat within 1dB because the circuit looks mostly resistive over the

frequency range. Is that okay?
MOSFET Driver Transformer Design…

M1’s 3 turn secondary give us only 4uH. No good.
Let’s use the M1 design and make the secondary the center-tapped (CT) output to the gates. Terminate each gate with a 33 Ω resistor to the CT.
The 33 Ω reflects to the primary as 33 x 4 = 132 Ω. This will be easier on the driver, BD139. We need 1.3 V to the gate, so 2.6 V peak, or 5.2 Vp-p will be

needed from the class A BD139 driver.
You can test these changes by driving the M1 primary directly from your signal generator. It should look very flat and stable.
The current transistor circuit seems to be very poor and needs re-design.

(because i don't understand these very well, can you re-design for me the M1 transformer connections, with the number of turns? Also please re-design the

BD139 stage.you said that the (CT) of secondary will be connected with gates by using 2 33ohm resistors? i don't understand this connection.
i can not find other ferrites here in Greece, but only FT50-43 [that ferrite i am using for M1] and BN-43-3312 [that ferrite i am using for M2] See the photos links to my previous posts)
thank you very much.

 

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